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f7b7c509d5
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efd3c1d154
3 changed files with 13 additions and 13 deletions
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@ -145,11 +145,11 @@ begin
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end
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MMIO_CSR_DATA_SIZE: begin
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csr_data_size <= $bits(csr_data_size)'((cp2af_sRxPort.c0.data + 63) >> 6);
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$display("%t: CSR_DATA_SIZE: %d", $time, $bits(csr_data_size)'((cp2af_sRxPort.c0.data + 63) >> 6));
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$display("%t: CSR_DATA_SIZE: %0d", $time, $bits(csr_data_size)'((cp2af_sRxPort.c0.data + 63) >> 6));
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end
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MMIO_CSR_CMD: begin
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csr_cmd <= $bits(csr_cmd)'(cp2af_sRxPort.c0.data);
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$display("%t: CSR_CMD: %d", $time, $bits(csr_cmd)'(cp2af_sRxPort.c0.data));
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$display("%t: CSR_CMD: %0d", $time, $bits(csr_cmd)'(cp2af_sRxPort.c0.data));
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end
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endcase
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end
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@ -175,7 +175,7 @@ begin
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16'h0006: af2cp_sTxPort.c2.data <= 64'h0; // next AFU
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16'h0008: af2cp_sTxPort.c2.data <= 64'h0; // reserved
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MMIO_CSR_STATUS: begin
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$display("%t: STATUS: state=%d", $time, state);
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$display("%t: STATUS: state=%0d", $time, state);
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af2cp_sTxPort.c2.data <= state;
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end
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default: af2cp_sTxPort.c2.data <= 64'h0;
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@ -209,11 +209,11 @@ begin
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STATE_IDLE: begin
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case (csr_cmd)
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CMD_TYPE_READ: begin
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$display("%t: CMD READ: ia=%h da=%h sz=%d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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$display("%t: CMD READ: ia=%h da=%h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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state <= STATE_READ;
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end
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CMD_TYPE_WRITE: begin
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$display("%t: CMD WRITE: ia=%h da=%h sz=%d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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$display("%t: CMD WRITE: ia=%h da=%h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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state <= STATE_WRITE;
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end
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CMD_TYPE_RUN: begin
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@ -222,7 +222,7 @@ begin
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state <= STATE_RUN;
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end
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CMD_TYPE_SNOOP: begin
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$display("%t: CMD SNOOP: da=%h sz=%d", $time, csr_mem_addr, csr_data_size);
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$display("%t: CMD SNOOP: da=%h sz=%0d", $time, csr_mem_addr, csr_data_size);
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state <= STATE_SNOOP1;
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end
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endcase
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@ -316,7 +316,7 @@ begin
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avs_address <= csr_mem_addr + avs_write_ctr;
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avs_write <= 1;
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avs_write_ctr <= avs_write_ctr + 1;
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$display("%t: AVS Wr Req: addr=%h value=%h", $time, csr_mem_addr + avs_write_ctr, cp2af_sRxPort.c0.data[63:0]);
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$display("%t: AVS Wr Req: addr=%h (%0d/%0d)", $time, csr_mem_addr + avs_write_ctr, avs_write_ctr + 1, csr_data_size);
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end
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end
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@ -337,7 +337,7 @@ begin
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avs_writedata <= {>>{vx_dram_req_data}};
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avs_address <= (vx_dram_req_addr >> 6);
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avs_write <= 1;
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$display("%t: AVS Wr Req: addr=%h value=%h", $time, vx_dram_req_addr >> 6, {vx_dram_req_data[1], vx_dram_req_data[0]});
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$display("%t: AVS Wr Req: addr=%h", $time, vx_dram_req_addr >> 6);
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end
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end
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endcase
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@ -447,7 +447,7 @@ begin
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if (cci_read_pending
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&& cp2af_sRxPort.c0.rspValid)
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begin
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$display("%t: CCI Rd Rsp: value=%h", $time, cp2af_sRxPort.c0.data[63:0]);
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$display("%t: CCI Rd Rsp", $time);
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cci_read_pending <= 0;
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end
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end
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@ -497,7 +497,7 @@ begin
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af2cp_sTxPort.c1.data <= t_ccip_clData'(avs_rdq_dout);
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af2cp_sTxPort.c1.valid <= 1;
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cci_write_pending <= 1;
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$display("%t: CCI Wr Req: addr=%h value=%h", $time, wr_hdr.address, avs_rdq_dout[63:0]);
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$display("%t: CCI Wr Req: addr=%h", $time, wr_hdr.address);
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end
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if (cci_write_pending
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@ -505,7 +505,7 @@ begin
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begin
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cci_write_ctr <= cci_write_ctr + 1;
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cci_write_pending <= 0;
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$display("%t: CCI Wr Rsp", $time);
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$display("%t: CCI Wr Rsp (%0d/%0d)", $time, cci_write_ctr + 1, csr_data_size);
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end
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end
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end
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@ -18,7 +18,7 @@ run-fpga: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
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run-ase: $(PROJECT)
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LIBOPAE_LOG=1 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
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LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
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run-rtlsim: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT)
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@ -46,7 +46,7 @@ run-fpga: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
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run-ase: $(PROJECT)
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LIBOPAE_LOG=1 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
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LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
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run-rtlsim: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
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