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arbiter refactoring

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This commit is contained in:
Blaise Tine 2024-07-14 00:44:35 -07:00
parent ad36bdbd44
commit f0ebe94253
9 changed files with 306 additions and 325 deletions
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91
hw/rtl/cache/VX_cache_bypass.sv vendored
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -18,16 +18,16 @@ module VX_cache_bypass #(
parameter TAG_SEL_IDX = 0,
parameter PASSTHRU = 0,
parameter NC_ENABLE = 0,
parameter NC_ENABLE = 0,
parameter WORD_SIZE = 1,
parameter LINE_SIZE = 1,
parameter LINE_SIZE = 1,
parameter CORE_ADDR_WIDTH = 1,
parameter CORE_TAG_WIDTH = 1,
parameter MEM_ADDR_WIDTH = 1,
parameter MEM_ADDR_WIDTH = 1,
parameter MEM_TAG_IN_WIDTH = 1,
parameter MEM_TAG_OUT_WIDTH = 1,
@ -35,9 +35,9 @@ module VX_cache_bypass #(
parameter CORE_OUT_BUF = 0,
parameter MEM_OUT_BUF = 0,
parameter CORE_DATA_WIDTH = WORD_SIZE * 8
) (
) (
input wire clk,
input wire reset,
@ -71,40 +71,39 @@ module VX_cache_bypass #(
wire core_req_nc_valid;
wire [NUM_REQS-1:0] core_req_nc_valids;
wire [NUM_REQS-1:0] core_req_nc_idxs;
wire [NUM_REQS-1:0] core_req_nc_idxs;
wire [`UP(REQ_SEL_BITS)-1:0] core_req_nc_idx;
wire [NUM_REQS-1:0] core_req_nc_sel;
wire [NUM_REQS-1:0] core_req_nc_sel;
wire core_req_nc_ready;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
if (PASSTHRU != 0) begin
assign core_req_nc_idxs[i] = 1'b1;
end else if (NC_ENABLE) begin
assign core_req_nc_idxs[i] = core_bus_in_if[i].req_data.atype[`ADDR_TYPE_IO];
end else begin
assign core_req_nc_idxs[i] = 1'b0;
end
end
assign core_req_nc_valids[i] = core_bus_in_if[i].req_valid && core_req_nc_idxs[i];
end
end
VX_generic_arbiter #(
.NUM_REQS (NUM_REQS),
.TYPE (PASSTHRU ? "R" : "P"),
.LOCK_ENABLE (1)
.TYPE (PASSTHRU ? "R" : "P")
) core_req_nc_arb (
.clk (clk),
.reset (reset),
.requests (core_req_nc_valids),
.reset (reset),
.requests (core_req_nc_valids),
.grant_index (core_req_nc_idx),
.grant_onehot (core_req_nc_sel),
.grant_valid (core_req_nc_valid),
.grant_unlock (core_req_nc_ready)
.grant_ready (core_req_nc_ready)
);
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_bus_out_if[i].req_valid = core_bus_in_if[i].req_valid && ~core_req_nc_idxs[i];
assign core_bus_out_if[i].req_data = core_bus_in_if[i].req_data;
assign core_bus_in_if[i].req_ready = core_req_nc_valids[i] ? (core_req_nc_ready && core_req_nc_sel[i])
assign core_bus_in_if[i].req_ready = core_req_nc_valids[i] ? (core_req_nc_ready && core_req_nc_sel[i])
: core_bus_out_if[i].req_ready;
end
@ -118,7 +117,7 @@ module VX_cache_bypass #(
wire [`CS_LINE_WIDTH-1:0] mem_req_out_data;
wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_out_tag;
wire mem_req_out_ready;
wire core_req_nc_sel_rw;
wire [WORD_SIZE-1:0] core_req_nc_sel_byteen;
wire [CORE_ADDR_WIDTH-1:0] core_req_nc_sel_addr;
@ -129,22 +128,22 @@ module VX_cache_bypass #(
wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_nc_mux_in[i] = {
core_bus_in_if[i].req_data.rw,
core_bus_in_if[i].req_data.rw,
core_bus_in_if[i].req_data.byteen,
core_bus_in_if[i].req_data.addr,
core_bus_in_if[i].req_data.atype,
core_bus_in_if[i].req_data.data,
core_bus_in_if[i].req_data.tag
core_bus_in_if[i].req_data.tag
};
end
assign {
core_req_nc_sel_rw,
core_req_nc_sel_byteen,
core_req_nc_sel_addr,
core_req_nc_sel_atype,
core_req_nc_sel_data,
core_req_nc_sel_tag
core_req_nc_sel_tag
} = core_req_nc_mux_in[core_req_nc_idx];
assign core_req_nc_ready = ~mem_bus_in_if.req_valid && mem_req_out_ready;
@ -157,11 +156,11 @@ module VX_cache_bypass #(
wire [MEM_TAG_ID_BITS-1:0] mem_req_tag_id_bypass;
wire [CORE_TAG_ID_BITS-1:0] core_req_in_id = core_req_nc_sel_tag[CORE_TAG_ID_BITS-1:0];
if (WORDS_PER_LINE > 1) begin
reg [WORDS_PER_LINE-1:0][WORD_SIZE-1:0] mem_req_byteen_in_r;
reg [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_r;
wire [WSEL_BITS-1:0] req_wsel = core_req_nc_sel_addr[WSEL_BITS-1:0];
always @(*) begin
@ -176,7 +175,7 @@ module VX_cache_bypass #(
assign mem_req_out_data = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.data : mem_req_data_in_r;
if (NUM_REQS > 1) begin
assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, req_wsel, core_req_in_id});
end else begin
end else begin
assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({req_wsel, core_req_in_id});
end
end else begin
@ -189,7 +188,7 @@ module VX_cache_bypass #(
end
end
wire [MEM_TAG_BYPASS_BITS-1:0] mem_req_tag_bypass;
wire [MEM_TAG_BYPASS_BITS-1:0] mem_req_tag_bypass;
if (UUID_WIDTH != 0) begin
assign mem_req_tag_bypass = {core_req_nc_sel_tag[CORE_TAG_ID_BITS +: UUID_WIDTH], mem_req_tag_id_bypass};
@ -202,7 +201,7 @@ module VX_cache_bypass #(
`UNUSED_VAR (mem_bus_in_if.req_data.tag)
end else begin
if (NC_ENABLE) begin
VX_bits_insert #(
VX_bits_insert #(
.N (MEM_TAG_OUT_WIDTH-1),
.S (1),
.POS (TAG_SEL_IDX)
@ -213,8 +212,8 @@ module VX_cache_bypass #(
);
end else begin
assign mem_req_out_tag = mem_bus_in_if.req_data.tag;
end
end
end
end
assign mem_bus_in_if.req_ready = mem_req_out_ready;
@ -225,11 +224,11 @@ module VX_cache_bypass #(
) mem_req_buf (
.clk (clk),
.reset (reset),
.valid_in (mem_req_out_valid),
.ready_in (mem_req_out_ready),
.valid_in (mem_req_out_valid),
.ready_in (mem_req_out_ready),
.data_in ({mem_req_out_rw, mem_req_out_byteen, mem_req_out_addr, mem_req_out_atype, mem_req_out_data, mem_req_out_tag}),
.data_out ({mem_bus_out_if.req_data.rw, mem_bus_out_if.req_data.byteen, mem_bus_out_if.req_data.addr, mem_bus_out_if.req_data.atype, mem_bus_out_if.req_data.data, mem_bus_out_if.req_data.tag}),
.valid_out (mem_bus_out_if.req_valid),
.valid_out (mem_bus_out_if.req_valid),
.ready_out (mem_bus_out_if.req_ready)
);
@ -253,7 +252,7 @@ module VX_cache_bypass #(
wire [(MEM_TAG_OUT_WIDTH - NC_ENABLE)-1:0] mem_rsp_tag_id_nc;
VX_bits_remove #(
VX_bits_remove #(
.N (MEM_TAG_OUT_WIDTH),
.S (NC_ENABLE),
.POS (TAG_SEL_IDX)
@ -265,10 +264,10 @@ module VX_cache_bypass #(
wire [`UP(REQ_SEL_BITS)-1:0] rsp_idx;
if (NUM_REQS > 1) begin
assign rsp_idx = mem_rsp_tag_id_nc[(CORE_TAG_ID_BITS + WSEL_BITS) +: REQ_SEL_BITS];
end else begin
end else begin
assign rsp_idx = 1'b0;
end
reg [NUM_REQS-1:0] rsp_nc_valid_r;
always @(*) begin
rsp_nc_valid_r = '0;
@ -277,13 +276,13 @@ module VX_cache_bypass #(
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_rsp_in_valid[i] = core_bus_out_if[i].rsp_valid || rsp_nc_valid_r[i];
assign core_bus_out_if[i].rsp_ready = core_rsp_in_ready[i];
assign core_bus_out_if[i].rsp_ready = core_rsp_in_ready[i];
end
if (WORDS_PER_LINE > 1) begin
wire [WSEL_BITS-1:0] rsp_wsel = mem_rsp_tag_id_nc[CORE_TAG_ID_BITS +: WSEL_BITS];
wire [WSEL_BITS-1:0] rsp_wsel = mem_rsp_tag_id_nc[CORE_TAG_ID_BITS +: WSEL_BITS];
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_rsp_in_data[i] = core_bus_out_if[i].rsp_valid ?
assign core_rsp_in_data[i] = core_bus_out_if[i].rsp_valid ?
core_bus_out_if[i].rsp_data.data : mem_bus_out_if.rsp_data.data[rsp_wsel * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
end
end else begin
@ -306,7 +305,7 @@ module VX_cache_bypass #(
assign core_rsp_in_tag[i] = core_bus_out_if[i].rsp_valid ? core_bus_out_if[i].rsp_data.tag : mem_rsp_tag_in_nc2;
end else begin
assign core_rsp_in_tag[i] = core_bus_out_if[i].rsp_data.tag;
end
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
@ -320,7 +319,7 @@ module VX_cache_bypass #(
.valid_in (core_rsp_in_valid[i]),
.ready_in (core_rsp_in_ready[i]),
.data_in ({core_rsp_in_data[i], core_rsp_in_tag[i]}),
.data_out ({core_bus_in_if[i].rsp_data.data, core_bus_in_if[i].rsp_data.tag}),
.data_out ({core_bus_in_if[i].rsp_data.data, core_bus_in_if[i].rsp_data.tag}),
.valid_out (core_bus_in_if[i].rsp_valid),
.ready_out (core_bus_in_if[i].rsp_ready)
);
@ -341,7 +340,7 @@ module VX_cache_bypass #(
assign mem_bus_in_if.rsp_data.data = mem_bus_out_if.rsp_data.data;
assign mem_bus_in_if.rsp_data.tag = mem_rsp_tag_id_nc;
end
wire [NUM_REQS-1:0] core_rsp_out_valid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_rsp_out_valid[i] = core_bus_out_if[i].rsp_valid;

25
hw/rtl/libs/VX_cyclic_arbiter.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -16,22 +16,21 @@
`TRACING_OFF
module VX_cyclic_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid,
input wire grant_unlock
input wire grant_ready
);
if (NUM_REQS == 1) begin
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (reset)
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
@ -45,10 +44,10 @@ module VX_cyclic_arbiter #(
always @(posedge clk) begin
if (reset) begin
grant_index_r <= '0;
end else begin
end else begin
if (!IS_POW2 && grant_index_r == LOG_NUM_REQS'(NUM_REQS-1)) begin
grant_index_r <= '0;
end else if (!LOCK_ENABLE || ~grant_valid || grant_unlock) begin
end else if (~grant_valid || grant_ready) begin
grant_index_r <= grant_index_r + LOG_NUM_REQS'(1);
end
end
@ -60,11 +59,11 @@ module VX_cyclic_arbiter #(
grant_onehot_r[grant_index_r] = 1'b1;
end
assign grant_index = grant_index_r;
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = requests[grant_index_r];
end
endmodule
`TRACING_ON

29
hw/rtl/libs/VX_fair_arbiter.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -16,28 +16,27 @@
`TRACING_OFF
module VX_fair_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid,
input wire grant_unlock
input wire grant_ready
);
if (NUM_REQS == 1) begin
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (grant_unlock)
`UNUSED_VAR (reset)
`UNUSED_VAR (grant_ready)
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
end else begin
reg [NUM_REQS-1:0] buffer;
@ -48,21 +47,21 @@ module VX_fair_arbiter #(
always @(posedge clk) begin
if (reset) begin
buffer <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
buffer <= buffer_n;
end
end
VX_priority_arbiter #(
.NUM_REQS (NUM_REQS)
) priority_arbiter (
.requests (requests_qual),
.requests (requests_qual),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_valid (grant_valid)
);
end
endmodule
`TRACING_ON

52
hw/rtl/libs/VX_generic_arbiter.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -16,29 +16,27 @@
`TRACING_OFF
module VX_generic_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter `STRING TYPE = "P",
parameter `STRING TYPE = "P",
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire reset,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid,
input wire grant_unlock
input wire grant_ready
);
if (TYPE == "P") begin
`UNUSED_PARAM (LOCK_ENABLE)
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (grant_unlock)
`UNUSED_VAR (grant_ready)
VX_priority_arbiter #(
.NUM_REQS (NUM_REQS)
) priority_arbiter (
.requests (requests),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot)
@ -47,68 +45,64 @@ module VX_generic_arbiter #(
end else if (TYPE == "R") begin
VX_rr_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE)
.NUM_REQS (NUM_REQS),
) rr_arbiter (
.clk (clk),
.reset (reset),
.requests (requests),
.reset (reset),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
.grant_ready (grant_ready)
);
end else if (TYPE == "F") begin
VX_fair_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE)
.NUM_REQS (NUM_REQS),
) fair_arbiter (
.clk (clk),
.reset (reset),
.requests (requests),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
.grant_ready (grant_ready)
);
end else if (TYPE == "M") begin
VX_matrix_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE)
.NUM_REQS (NUM_REQS),
) matrix_arbiter (
.clk (clk),
.reset (reset),
.requests (requests),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
.grant_ready (grant_ready)
);
end else if (TYPE == "C") begin
VX_cyclic_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE)
.NUM_REQS (NUM_REQS),
) cyclic_arbiter (
.clk (clk),
.reset (reset),
.requests (requests),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_unlock (grant_unlock)
.grant_ready (grant_ready)
);
end else begin
`ERROR(("invalid parameter"));
end
endmodule
`TRACING_ON

56
hw/rtl/libs/VX_matrix_arbiter.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -16,52 +16,51 @@
`TRACING_OFF
module VX_matrix_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire reset,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid,
input wire grant_unlock
input wire grant_ready
);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (grant_unlock)
`UNUSED_VAR (grant_ready)
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
reg [NUM_REQS-1:1] state [NUM_REQS-1:0];
reg [NUM_REQS-1:1] state [NUM_REQS-1:0];
wire [NUM_REQS-1:0] pri [NUM_REQS-1:0];
wire [NUM_REQS-1:0] grant_unqual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
end
end
else if (j < i) begin
assign pri[j][i] = requests[i] && !state[j][i];
end
end
else begin
assign pri[j][i] = 0;
assign pri[j][i] = 0;
end
end
assign grant_unqual[i] = requests[i] && !(| pri[i]);
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = i + 1; j < NUM_REQS; ++j) begin
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= '0;
end else begin
state[i][j] <= (state[i][j] || grant_unqual[j]) && !grant_unqual[i];
@ -70,20 +69,15 @@ module VX_matrix_arbiter #(
end
end
if (LOCK_ENABLE == 0) begin
`UNUSED_VAR (grant_unlock)
assign grant_onehot = grant_unqual;
end else begin
reg [NUM_REQS-1:0] grant_unqual_prev;
always @(posedge clk) begin
if (reset) begin
grant_unqual_prev <= '0;
end else if (grant_unlock) begin
grant_unqual_prev <= grant_unqual;
end
reg [NUM_REQS-1:0] grant_unqual_prev;
always @(posedge clk) begin
if (reset) begin
grant_unqual_prev <= '0;
end else if (grant_ready) begin
grant_unqual_prev <= grant_unqual;
end
assign grant_onehot = grant_unlock ? grant_unqual : grant_unqual_prev;
end
assign grant_onehot = grant_ready ? grant_unqual : grant_unqual_prev;
VX_onehot_encoder #(
.N (NUM_REQS)
@ -96,6 +90,6 @@ module VX_matrix_arbiter #(
assign grant_valid = (| requests);
end
endmodule
`TRACING_ON

10
hw/rtl/libs/VX_priority_arbiter.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -23,8 +23,8 @@ module VX_priority_arbiter #(
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
);
if (NUM_REQS == 1) begin
if (NUM_REQS == 1) begin
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
@ -41,6 +41,6 @@ module VX_priority_arbiter #(
);
end
endmodule
`TRACING_ON

309
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -16,24 +16,23 @@
`TRACING_OFF
module VX_rr_arbiter #(
parameter NUM_REQS = 1,
parameter LOCK_ENABLE = 0,
parameter MODEL = 1,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire reset,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid,
input wire grant_unlock
input wire grant_ready
);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (grant_unlock)
`UNUSED_VAR (grant_ready)
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
@ -41,7 +40,7 @@ module VX_rr_arbiter #(
end else if (NUM_REQS == 2) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
@ -52,279 +51,279 @@ module VX_rr_arbiter #(
endcase
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end /*else if (NUM_REQS == 3) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
5'b00_001,
5'b01_0?1,
5'b01_0?1,
5'b10_??1: begin grant_onehot_r = 3'b001; grant_index_r = LOG_NUM_REQS'(0); end
5'b00_?1?,
5'b01_010,
5'b00_?1?,
5'b01_010,
5'b10_?10: begin grant_onehot_r = 3'b010; grant_index_r = LOG_NUM_REQS'(1); end
default: begin grant_onehot_r = 3'b100; grant_index_r = LOG_NUM_REQS'(2); end
endcase
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end */else if (NUM_REQS == 4) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
6'b00_0001,
6'b01_00?1,
6'b00_0001,
6'b01_00?1,
6'b10_0??1,
6'b11_???1: begin grant_onehot_r = 4'b0001; grant_index_r = LOG_NUM_REQS'(0); end
6'b00_??1?,
6'b01_0010,
6'b10_0?10,
6'b00_??1?,
6'b01_0010,
6'b10_0?10,
6'b11_??10: begin grant_onehot_r = 4'b0010; grant_index_r = LOG_NUM_REQS'(1); end
6'b00_?10?,
6'b01_?1??,
6'b10_0100,
6'b00_?10?,
6'b01_?1??,
6'b10_0100,
6'b11_?100: begin grant_onehot_r = 4'b0100; grant_index_r = LOG_NUM_REQS'(2); end
default: begin grant_onehot_r = 4'b1000; grant_index_r = LOG_NUM_REQS'(3); end
endcase
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end /*else if (NUM_REQS == 5) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
8'b000_00001,
8'b001_000?1,
8'b010_00??1,
8'b000_00001,
8'b001_000?1,
8'b010_00??1,
8'b011_0???1,
8'b100_????1: begin grant_onehot_r = 5'b00001; grant_index_r = LOG_NUM_REQS'(0); end
8'b000_???1?,
8'b001_00010,
8'b010_00?10,
8'b011_0??10,
8'b000_???1?,
8'b001_00010,
8'b010_00?10,
8'b011_0??10,
8'b100_???10: begin grant_onehot_r = 5'b00010; grant_index_r = LOG_NUM_REQS'(1); end
8'b000_??10?,
8'b001_??1??,
8'b010_00100,
8'b000_??10?,
8'b001_??1??,
8'b010_00100,
8'b011_0?100,
8'b100_??100: begin grant_onehot_r = 5'b00100; grant_index_r = LOG_NUM_REQS'(2); end
8'b000_?100?,
8'b001_?10??,
8'b000_?100?,
8'b001_?10??,
8'b010_?1???,
8'b011_01000,
8'b011_01000,
8'b100_?1000: begin grant_onehot_r = 5'b01000; grant_index_r = LOG_NUM_REQS'(3); end
default: begin grant_onehot_r = 5'b10000; grant_index_r = LOG_NUM_REQS'(4); end
endcase
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end else if (NUM_REQS == 6) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
9'b000_000001,
9'b001_0000?1,
9'b010_000??1,
9'b011_00???1,
9'b100_0????1,
9'b000_000001,
9'b001_0000?1,
9'b010_000??1,
9'b011_00???1,
9'b100_0????1,
9'b101_?????1: begin grant_onehot_r = 6'b000001; grant_index_r = LOG_NUM_REQS'(0); end
9'b000_????1?,
9'b001_000010,
9'b010_000?10,
9'b011_00??10,
9'b100_0???10,
9'b000_????1?,
9'b001_000010,
9'b010_000?10,
9'b011_00??10,
9'b100_0???10,
9'b101_????10: begin grant_onehot_r = 6'b000010; grant_index_r = LOG_NUM_REQS'(1); end
9'b000_???10?,
9'b001_???1??,
9'b010_000100,
9'b000_???10?,
9'b001_???1??,
9'b010_000100,
9'b011_00?100,
9'b100_0??100,
9'b100_0??100,
9'b101_???100: begin grant_onehot_r = 6'b000100; grant_index_r = LOG_NUM_REQS'(2); end
9'b000_??100?,
9'b001_??10??,
9'b000_??100?,
9'b001_??10??,
9'b010_??1???,
9'b011_001000,
9'b100_0?1000,
9'b011_001000,
9'b100_0?1000,
9'b101_??1000: begin grant_onehot_r = 6'b001000; grant_index_r = LOG_NUM_REQS'(3); end
9'b000_?1000?,
9'b001_?100??,
9'b000_?1000?,
9'b001_?100??,
9'b010_?10???,
9'b011_?1????,
9'b100_010000,
9'b011_?1????,
9'b100_010000,
9'b101_?10000: begin grant_onehot_r = 6'b010000; grant_index_r = LOG_NUM_REQS'(4); end
default: begin grant_onehot_r = 6'b100000; grant_index_r = LOG_NUM_REQS'(5); end
endcase
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end else if (NUM_REQS == 7) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
10'b000_000001,
10'b001_0000?1,
10'b010_000??1,
10'b011_00???1,
10'b100_00???1,
10'b101_0????1,
10'b000_000001,
10'b001_0000?1,
10'b010_000??1,
10'b011_00???1,
10'b100_00???1,
10'b101_0????1,
10'b110_?????1: begin grant_onehot_r = 7'b0000001; grant_index_r = LOG_NUM_REQS'(0); end
10'b000_?????1?,
10'b001_0000010,
10'b010_0000?10,
10'b011_000??10,
10'b100_00???10,
10'b101_0????10,
10'b000_?????1?,
10'b001_0000010,
10'b010_0000?10,
10'b011_000??10,
10'b100_00???10,
10'b101_0????10,
10'b110_?????10: begin grant_onehot_r = 7'b0000010; grant_index_r = LOG_NUM_REQS'(1); end
10'b000_????10?,
10'b001_????1??,
10'b010_0000100,
10'b000_????10?,
10'b001_????1??,
10'b010_0000100,
10'b011_000?100,
10'b100_00??100,
10'b101_0???100,
10'b100_00??100,
10'b101_0???100,
10'b110_????100: begin grant_onehot_r = 7'b0000100; grant_index_r = LOG_NUM_REQS'(2); end
10'b000_???100?,
10'b001_???10??,
10'b000_???100?,
10'b001_???10??,
10'b010_???1???,
10'b011_0001000,
10'b100_00?1000,
10'b101_0??1000,
10'b011_0001000,
10'b100_00?1000,
10'b101_0??1000,
10'b110_???1000: begin grant_onehot_r = 7'b0001000; grant_index_r = LOG_NUM_REQS'(3); end
10'b000_??1000?,
10'b001_??100??,
10'b000_??1000?,
10'b001_??100??,
10'b010_??10???,
10'b011_??1????,
10'b100_0010000,
10'b101_0?10000,
10'b011_??1????,
10'b100_0010000,
10'b101_0?10000,
10'b110_??10000: begin grant_onehot_r = 7'b0010000; grant_index_r = LOG_NUM_REQS'(4); end
10'b000_?10000?,
10'b001_?1000??,
10'b000_?10000?,
10'b001_?1000??,
10'b010_?100???,
10'b011_?10????,
10'b100_?1?????,
10'b101_0100000,
10'b011_?10????,
10'b100_?1?????,
10'b101_0100000,
10'b110_?100000: begin grant_onehot_r = 7'b0100000; grant_index_r = LOG_NUM_REQS'(5); end
default: begin grant_onehot_r = 7'b1000000; grant_index_r = LOG_NUM_REQS'(6); end
endcase
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end */else if (NUM_REQS == 8) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
11'b000_00000001,
11'b001_000000?1,
11'b010_00000??1,
11'b000_00000001,
11'b001_000000?1,
11'b010_00000??1,
11'b011_0000???1,
11'b100_000????1,
11'b101_00?????1,
11'b110_0??????1,
11'b100_000????1,
11'b101_00?????1,
11'b110_0??????1,
11'b111_???????1: begin grant_onehot_r = 8'b00000001; grant_index_r = LOG_NUM_REQS'(0); end
11'b000_??????1?,
11'b001_00000010,
11'b010_00000?10,
11'b000_??????1?,
11'b001_00000010,
11'b010_00000?10,
11'b011_0000??10,
11'b100_000???10,
11'b101_00????10,
11'b110_0?????10,
11'b100_000???10,
11'b101_00????10,
11'b110_0?????10,
11'b111_??????10: begin grant_onehot_r = 8'b00000010; grant_index_r = LOG_NUM_REQS'(1); end
11'b000_?????10?,
11'b001_?????1??,
11'b010_00000100,
11'b000_?????10?,
11'b001_?????1??,
11'b010_00000100,
11'b011_0000?100,
11'b100_000??100,
11'b101_00???100,
11'b110_0????100,
11'b100_000??100,
11'b101_00???100,
11'b110_0????100,
11'b111_?????100: begin grant_onehot_r = 8'b00000100; grant_index_r = LOG_NUM_REQS'(2); end
11'b000_????100?,
11'b001_????10??,
@ -362,20 +361,20 @@ module VX_rr_arbiter #(
endcase
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end else if (MODEL == 1) begin
`IGNORE_UNOPTFLAT_BEGIN
wire [NUM_REQS-1:0] mask_higher_pri_regs, unmask_higher_pri_regs;
`IGNORE_UNOPTFLAT_END
@ -399,7 +398,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
pointer_reg <= {NUM_REQS{1'b1}};
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
if (|req_masked) begin
pointer_reg <= mask_higher_pri_regs;
end else if (|requests) begin
@ -410,22 +409,22 @@ module VX_rr_arbiter #(
end
end
assign grant_valid = (| requests);
assign grant_valid = (| requests);
VX_onehot_encoder #(
.N (NUM_REQS)
) onehot_encoder (
.data_in (grant_onehot),
.data_out (grant_index),
.data_out (grant_index),
`UNUSED_PIN (valid_out)
);
end else begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] state;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0] state;
always @(*) begin
grant_index_r = 'x;
grant_onehot_r = 'x;
@ -440,18 +439,18 @@ module VX_rr_arbiter #(
end
end
always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin
if (reset) begin
state <= '0;
end else if (!LOCK_ENABLE || grant_unlock) begin
end else if (grant_ready) begin
state <= grant_index_r;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
assign grant_valid = (| requests);
end
endmodule
`TRACING_ON

16
hw/rtl/libs/VX_stream_arb.sv
View file

@ -161,9 +161,8 @@ module VX_stream_arb #(
wire arb_ready;
VX_generic_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (1),
.TYPE (ARBITER)
.NUM_REQS (NUM_REQS),
.TYPE (ARBITER)
) arbiter (
.clk (clk),
.reset (reset),
@ -171,7 +170,7 @@ module VX_stream_arb #(
.grant_valid (arb_valid),
.grant_index (arb_index),
.grant_onehot (arb_onehot),
.grant_unlock (arb_ready)
.grant_ready (arb_ready)
);
assign valid_in_r = arb_valid;
@ -309,17 +308,16 @@ module VX_stream_arb #(
wire arb_ready;
VX_generic_arbiter #(
.NUM_REQS (NUM_OUTPUTS),
.LOCK_ENABLE (1),
.TYPE (ARBITER)
.NUM_REQS (NUM_OUTPUTS),
.TYPE (ARBITER)
) arbiter (
.clk (clk),
.reset (reset),
.requests (arb_requests),
.grant_valid (arb_valid),
`UNUSED_PIN (grant_index),
`UNUSED_PIN (grant_index),
.grant_onehot (arb_onehot),
.grant_unlock (arb_ready)
.grant_ready (arb_ready)
);
assign arb_requests = ready_in_r;

43
hw/rtl/libs/VX_stream_pack.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -15,9 +15,9 @@
`TRACING_OFF
module VX_stream_pack #(
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
parameter TAG_WIDTH = 1,
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
parameter TAG_WIDTH = 1,
parameter TAG_SEL_BITS = 0,
parameter `STRING ARBITER = "P",
parameter OUT_BUF = 0
@ -48,16 +48,15 @@ module VX_stream_pack #(
VX_generic_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (1),
.TYPE (ARBITER)
.TYPE (ARBITER)
) arbiter (
.clk (clk),
.reset (reset),
.requests (valid_in),
.requests (valid_in),
.grant_valid (grant_valid),
.grant_index (grant_index),
`UNUSED_PIN (grant_onehot),
.grant_unlock(grant_ready)
`UNUSED_PIN (grant_onehot),
.grant_ready (grant_ready)
);
reg [NUM_REQS-1:0] valid_sel;
@ -65,20 +64,20 @@ module VX_stream_pack #(
wire ready_unqual;
wire [TAG_WIDTH-1:0] tag_sel = tag_in[grant_index];
always @(*) begin
valid_sel = '0;
ready_sel = '0;
always @(*) begin
valid_sel = '0;
ready_sel = '0;
for (integer i = 0; i < NUM_REQS; ++i) begin
if (tag_in[i][TAG_SEL_BITS-1:0] == tag_sel[TAG_SEL_BITS-1:0]) begin
valid_sel[i] = valid_in[i];
valid_sel[i] = valid_in[i];
ready_sel[i] = ready_unqual;
end
end
end
end
assign grant_ready = ready_unqual;
VX_elastic_buffer #(
.DATAW (NUM_REQS + TAG_WIDTH + (NUM_REQS * DATA_WIDTH)),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
@ -86,16 +85,16 @@ module VX_stream_pack #(
) out_buf (
.clk (clk),
.reset (reset),
.valid_in (grant_valid),
.valid_in (grant_valid),
.data_in ({valid_sel, tag_sel, data_in}),
.ready_in (ready_unqual),
.ready_in (ready_unqual),
.valid_out (valid_out),
.data_out ({mask_out, tag_out, data_out}),
.ready_out (ready_out)
);
);
assign ready_in = ready_sel;
assign ready_in = ready_sel;
end else begin
`UNUSED_VAR (clk)