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Add multi-cycle compat module and use it in ALU
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wgulian3
parent
83d1f54fcf
commit
f2c0453702
3 changed files with 141 additions and 22 deletions
58
rtl/VX_alu.v
58
rtl/VX_alu.v
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@ -14,13 +14,17 @@ module VX_alu(
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output reg out_alu_stall
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);
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localparam div_pipeline_len = 10;
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localparam div_pipeline_len = 10;
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localparam mul_pipeline_len = 3;
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wire[31:0] unsigned_div_result;
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wire[31:0] unsigned_div_result;
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wire[31:0] unsigned_rem_result;
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wire[31:0] signed_div_result;
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wire[31:0] signed_rem_result;
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wire[63:0] mul_data_a, mul_data_b;
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wire[63:0] mul_result;
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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@ -53,6 +57,28 @@ module VX_alu(
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.remainder(signed_rem_result)
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);
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VX_mult #(
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.WIDTHA(64),
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.WIDTHB(64),
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.WIDTHP(64),
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.SPEED("HIGHEST"),
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.PIPELINE(mul_pipeline_len)
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) multiplier (
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.clock(clk),
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.aclr(1'b0),
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.clken(1'b1), // TODO this could be disabled on inactive instructions
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.dataa(mul_data_a),
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.datab(mul_data_b),
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.result(mul_result)
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);
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// MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned)
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wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
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wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2};
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assign mul_data_a = (in_alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed;
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assign mul_data_b = (in_alu_op == `MULHU || in_alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed;
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reg [15:0] curr_inst_delay;
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reg [15:0] inst_delay;
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reg inst_was_stalling;
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@ -66,6 +92,10 @@ module VX_alu(
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`DIVU,
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`REM,
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`REMU: curr_inst_delay = div_pipeline_len;
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`MUL,
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`MULH,
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`MULHSU,
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`MULHU: curr_inst_delay = mul_pipeline_len;
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default: curr_inst_delay = 0;
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endcase // in_alu_op
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end
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@ -95,8 +125,6 @@ module VX_alu(
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wire[31:0] ALU_in1;
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wire[31:0] ALU_in2;
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wire[63:0] ALU_in1_mult;
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wire[63:0] ALU_in2_mult;
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wire[31:0] upper_immed;
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assign which_in2 = in_rs2_src == `RS2_IMMED;
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@ -106,20 +134,6 @@ module VX_alu(
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assign upper_immed = {in_upper_immed, {12{1'b0}}};
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//always @(posedge `MUL) begin
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/* verilator lint_off UNUSED */
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wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
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wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2};
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assign ALU_in1_mult = (in_alu_op == `MULHU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in1} : alu_in1_signed;
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assign ALU_in2_mult = (in_alu_op == `MULHU || in_alu_op == `MULHSU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in2} : alu_in2_signed;
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wire[63:0] mult_result = ALU_in1_mult * ALU_in2_mult;
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/* verilator lint_on UNUSED */
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always @(in_alu_op or ALU_in1 or ALU_in2) begin
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case(in_alu_op)
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`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
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@ -135,11 +149,11 @@ module VX_alu(
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`SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
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`LUI_ALU: out_alu_result = upper_immed;
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`AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
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`MUL: out_alu_result = mult_result[31:0];
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`MULH: out_alu_result = mult_result[63:32];
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`MULHSU: out_alu_result = mult_result[63:32];
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`MULHU: out_alu_result = mult_result[63:32];
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// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
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`MUL: out_alu_result = mul_result[31:0];
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`MULH: out_alu_result = mul_result[63:32];
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`MULHSU: out_alu_result = mul_result[63:32];
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`MULHU: out_alu_result = mul_result[63:32];
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`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
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`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
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`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
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104
rtl/compat/VX_mult.v
Normal file
104
rtl/compat/VX_mult.v
Normal file
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@ -0,0 +1,104 @@
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module VX_mult
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#(
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parameter WIDTHA=1,
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parameter WIDTHB=1,
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parameter WIDTHP=1,
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parameter REP="UNSIGNED",
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parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
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parameter PIPELINE=0
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)
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(
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input clock, aclr, clken,
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input [WIDTHA-1:0] dataa,
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input [WIDTHB-1:0] datab,
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output reg [WIDTHP-1:0] result
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);
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// synthesis read_comments_as_HDL on
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// localparam IMPL = "quartus";
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// synthesis read_comments_as_HDL off
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// altera translate_off
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localparam IMPL="fallback";
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// altera translate_on
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generate
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if (IMPL == "quartus") begin
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localparam lpm_speed=SPEED == "HIGHEST" ? 10:5;
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lpm_mult#(
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.LPM_WIDTHA(WIDTHA),
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.LPM_WIDTHB(WIDTHB),
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.LPM_WIDTHP(WIDTHP),
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.LPM_REPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.MAXIMIZE_SPEED(lpm_speed)
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) quartus_mult(
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.clock(clock),
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.aclr(aclr),
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.clken(clken),
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.dataa(dataa),
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.datab(datab),
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.result(result)
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);
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end
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else begin
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wire [WIDTHA-1:0] dataa_pipe_end;
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wire [WIDTHB-1:0] datab_pipe_end;
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if (PIPELINE == 0) begin
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assign dataa_pipe_end = dataa;
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assign datab_pipe_end = datab;
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end else begin
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reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
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reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
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genvar pipe_stage;
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for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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dataa_pipe[pipe_stage+1] <= 0;
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datab_pipe[pipe_stage+1] <= 0;
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end
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else if (clken) begin
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dataa_pipe[pipe_stage+1] <= dataa_pipe[pipe_stage];
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datab_pipe[pipe_stage+1] <= datab_pipe[pipe_stage];
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end
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end
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end
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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dataa_pipe[0] <= 0;
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datab_pipe[0] <= 0;
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end
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else if (clken) begin
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dataa_pipe[0] <= dataa;
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datab_pipe[0] <= datab;
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end
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end
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assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
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assign datab_pipe_end = datab_pipe[PIPELINE-1];
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end
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/* * * * * * * * * * * * * * * * * * * * * * */
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/* Do the actual fallback computation here */
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/* * * * * * * * * * * * * * * * * * * * * * */
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if (REP == "SIGNED") begin
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assign result = $signed($signed(dataa_pipe_end) * $signed(datab_pipe_end));
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end
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else begin
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assign result = dataa_pipe_end * datab_pipe_end;
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end
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end
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endgenerate
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endmodule : VX_mult
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@ -71,6 +71,7 @@ set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v
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set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v
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set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v
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set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v
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set_global_assignment -name VERILOG_FILE ../compat/VX_mult.v
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set_global_assignment -name VERILOG_FILE ../VX_alu.v
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set_global_assignment -name VERILOG_FILE ../VX_back_end.v
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set_global_assignment -name VERILOG_FILE ../VX_context.v
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