github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor update

Browse source
This commit is contained in:
Blaise Tine 2024-09-27 10:02:59 -07:00
parent 533ddffc47
commit f2c970868e
1 changed files with 4 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

9
hw/rtl/libs/VX_mem_scheduler.sv
View file

@ -459,16 +459,16 @@ module VX_mem_scheduler #(
end else begin : g_rsp_full
// use flattened arrays for BRAM synthesis compatibility
reg [(CORE_BATCHES * CORE_CHANNELS * WORD_WIDTH)-1:0] rsp_store [CORE_QUEUE_SIZE-1:0];
reg [(CORE_BATCHES * CORE_CHANNELS * WORD_WIDTH)-1:0] rsp_store_n; // use flattened array for BRAM synthesis compatibility
reg [(CORE_BATCHES * CORE_CHANNELS)-1:0][WORD_WIDTH-1:0] rsp_store_n;
reg [CORE_REQS-1:0] rsp_orig_mask [CORE_QUEUE_SIZE-1:0];
always @(*) begin
rsp_store_n = rsp_store[ibuf_raddr];
for (integer i = 0; i < CORE_CHANNELS; ++i) begin
if ((CORE_CHANNELS == 1) || mem_rsp_mask_s[i]) begin
integer k = (rsp_batch_idx * CORE_CHANNELS * WORD_WIDTH) + (i * WORD_WIDTH);
rsp_store_n[k +: WORD_WIDTH] = mem_rsp_data_s[i];
rsp_store_n[rsp_batch_idx * CORE_CHANNELS + i] = mem_rsp_data_s[i];
end
end
end
@ -489,8 +489,7 @@ module VX_mem_scheduler #(
for (genvar r = 0; r < CORE_REQS; ++r) begin : g_crsp_data
localparam i = r / CORE_CHANNELS;
localparam j = r % CORE_CHANNELS;
localparam k = (i * CORE_CHANNELS * WORD_WIDTH) + (j * WORD_WIDTH);
assign crsp_data[r] = rsp_store_n[k +: WORD_WIDTH];
assign crsp_data[r] = rsp_store_n[i * CORE_CHANNELS + j];
end
assign mem_rsp_ready_s = crsp_ready || ~rsp_complete;