minor update

README.md

@@ -46,6 +46,15 @@ Vortex is a full-system RISCV-based GPGPU processor.
     $ cd Vortex
 ### Install prebuilt toolchain
     $ ./ci/toolchain_install.sh -all
+
+    By default, the toolchain will install to /opt folder. You can install the toolchain to a different directory by overiding DESTDIR.
+
+    $ DESTDIR=$TOOLDIR ./ci/toolchain_install.sh -all
+    $ export VORTEX_HOME=$TOOLDIR/vortex-gfx
+    $ export LLVM_VORTEX=$TOOLDIR/llvm-vortex
+    $ export RISCV_TOOLCHAIN_PATH=$TOOLDIR/riscv-gnu-toolchain
+    $ export VERILATOR_ROOT=$TOOLDIR/verilator
+    $ export PATH=$VERILATOR_ROOT/bin:$PATH 
 ### Build Vortex sources
     $ make -s
 ### Quick demo running vecadd OpenCL kernel on 2 cores

docs/fpga_setup.md

@@ -17,20 +17,13 @@ OPAE Build
 ------------------
 
 The FPGA has to following configuration options:
-- 1 core fpga (fpga-1c)
-- 2 cores fpga (fpga-2c)
-- 4 cores fpga (fpga-4c)
-- 8 cores fpga (fpga-8c)
-- 16 cores fpga (fpga-16c)
-- 32 cores fpga (fpga-32c)
-- 64 cores fpga (fpga-64c)
+- DEVICE_FAMILY=arria10 | stratix10
+- NUM_CORES=#n
 
 Command line:
 
     $ cd hw/syn/opae
-    $ make fpga-<num-of-cores>c
-
-Example: `make fpga-4c`
+    $ NUM_CORES=4 make build
 
 A new folder (ex: `build_fpga_4c`) will be created and the build will start and take ~30-480 min to complete.
 
@@ -45,7 +38,7 @@ The hardware configuration file `/hw/rtl/VX_config.vh` defines all the hardware
 
 You configure the syntesis build from the command line:
 
-    $ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make fpga-4c
+    $ CONFIGS="-DPERF_ENABLE -DNUM_THREADS=8" make build
 
 OPAE Build Progress
 -------------------
@@ -58,12 +51,9 @@ Check if the build is still running by looking for quartus_sh, quartus_syn, or q
 
     $ ps -u <username>
 
-
 If the build fails and you need to restart it, clean up the build folder using the following command:
 
-    $ make clean-fpga-<num-of-cores>c
-
-Example: `make clean-fpga-4c`
+    $ make clean
 
 The file `vortex_afu.gbs` should exist when the build is done:
 

runtime/common/vx_utils.cpp

@@ -622,6 +622,8 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) {
   }
 #endif
 
+  fflush(stream);
+
   // release allocated resources
   vx_buf_free(staging_buf);
 

runtime/simx/vortex.cpp

@@ -108,9 +108,9 @@ public:
 
         ram_.write((const uint8_t*)src + src_offset, dest_addr, asize);
         
-        /*BGPRINT("upload %d bytes to 0x%x\n", size, dest_addr);
-        for (int i = 0; i < size; i += 4) {
-            DBGPRINT("  0x%x <- 0x%x\n", dest_addr + i, *(uint32_t*)((uint8_t*)src + src_offset + i));
+        /*DBGPRINT("upload %ld bytes to 0x%lx\n", size, dest_addr);
+        for (uint64_t i = 0; i < size && i < 1024; i += 4) {
+            DBGPRINT("  0x%lx <- 0x%x\n", dest_addr + i, *(uint32_t*)((uint8_t*)src + src_offset + i));
         }*/
         
         return 0;
@@ -123,9 +123,9 @@ public:
 
         ram_.read((uint8_t*)dest + dest_offset, src_addr, asize);
         
-        /*DBGPRINT("download %d bytes from 0x%x\n", size, src_addr);
-        for (int i = 0; i < size; i += 4) {
-            DBGPRINT("  0x%x -> 0x%x\n", src_addr + i, *(uint32_t*)((uint8_t*)dest + dest_offset + i));
+        /*DBGPRINT("download %ld bytes from 0x%lx\n", size, src_addr);
+        for (uint64_t i = 0; i < size && i < 1024; i += 4) {
+            DBGPRINT("  0x%lx -> 0x%x\n", src_addr + i, *(uint32_t*)((uint8_t*)dest + dest_offset + i));
         }*/
         
         return 0;
@@ -361,7 +361,7 @@ extern int vx_start(vx_device_h hdevice) {
     if (nullptr == hdevice)
         return -1;    
     
-    DBGPRINT("START");
+    DBGPRINT("START\n");
 
     vx_device *device = ((vx_device*)hdevice);