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remove unsued cache parameter LLVQ_SIZE

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This commit is contained in:
Blaise Tine 2020-05-23 00:33:51 -04:00
parent 70dadca9fe
commit f3b21aab8f
6 changed files with 0 additions and 35 deletions
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25
hw/rtl/VX_config.vh
View file

@ -135,11 +135,6 @@
`define DDFQQ_SIZE `DREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef DLLVQ_SIZE
`define DLLVQ_SIZE 0
`endif
// Prefetcher
`ifndef DPRFQ_SIZE
`define DPRFQ_SIZE 32
@ -211,11 +206,6 @@
`define IDFQQ_SIZE `IREQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef ILLVQ_SIZE
`define ILLVQ_SIZE 16
`endif
// Prefetcher
`ifndef IPRFQ_SIZE
`define IPRFQ_SIZE 32
@ -287,11 +277,6 @@
`define SDFQQ_SIZE 16
`endif
// Lower Level Cache Hit Queue Size
`ifndef SLLVQ_SIZE
`define SLLVQ_SIZE 16
`endif
// Prefetcher
`ifndef SPRFQ_SIZE
`define SPRFQ_SIZE 4
@ -368,11 +353,6 @@
`define L2DFQQ_SIZE `L2REQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef L2LLVQ_SIZE
`define L2LLVQ_SIZE 32
`endif
// Prefetcher
`ifndef L2PRFQ_SIZE
`define L2PRFQ_SIZE 32
@ -449,11 +429,6 @@
`define L3DFQQ_SIZE `L3REQQ_SIZE
`endif
// Lower Level Cache Hit Queue Size
`ifndef L3LLVQ_SIZE
`define L3LLVQ_SIZE 0
`endif
// Prefetcher
`ifndef L3PRFQ_SIZE
`define L3PRFQ_SIZE 32

3
hw/rtl/VX_dmem_ctrl.v
View file

@ -66,7 +66,6 @@ module VX_dmem_ctrl # (
.CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (`SDWBQ_SIZE),
.DFQQ_SIZE (`SDFQQ_SIZE),
.LLVQ_SIZE (`SLLVQ_SIZE),
.PRFQ_SIZE (`SPRFQ_SIZE),
.PRFQ_STRIDE (`SPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE),
@ -147,7 +146,6 @@ module VX_dmem_ctrl # (
.CWBQ_SIZE (`DCWBQ_SIZE),
.DWBQ_SIZE (`DDWBQ_SIZE),
.DFQQ_SIZE (`DDFQQ_SIZE),
.LLVQ_SIZE (`DLLVQ_SIZE),
.PRFQ_SIZE (`DPRFQ_SIZE),
.PRFQ_STRIDE (`DPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
@ -229,7 +227,6 @@ module VX_dmem_ctrl # (
.CWBQ_SIZE (`ICWBQ_SIZE),
.DWBQ_SIZE (`IDWBQ_SIZE),
.DFQQ_SIZE (`IDFQQ_SIZE),
.LLVQ_SIZE (`ILLVQ_SIZE),
.PRFQ_SIZE (`IPRFQ_SIZE),
.PRFQ_STRIDE (`IPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE),

1
hw/rtl/Vortex_Cluster.v
View file

@ -250,7 +250,6 @@ module Vortex_Cluster #(
.CWBQ_SIZE (`L2CWBQ_SIZE),
.DWBQ_SIZE (`L2DWBQ_SIZE),
.DFQQ_SIZE (`L2DFQQ_SIZE),
.LLVQ_SIZE (`L2LLVQ_SIZE),
.PRFQ_SIZE (`L2PRFQ_SIZE),
.PRFQ_STRIDE (`L2PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),

1
hw/rtl/Vortex_Socket.v
View file

@ -258,7 +258,6 @@ module Vortex_Socket (
.CWBQ_SIZE (`L3CWBQ_SIZE),
.DWBQ_SIZE (`L3DWBQ_SIZE),
.DFQQ_SIZE (`L3DFQQ_SIZE),
.LLVQ_SIZE (`L3LLVQ_SIZE),
.PRFQ_SIZE (`L3PRFQ_SIZE),
.PRFQ_STRIDE (`L3PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),

2
hw/rtl/cache/VX_bank.v vendored
View file

@ -33,8 +33,6 @@ module VX_bank #(
parameter DWBQ_SIZE = 0,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 0,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 0,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 0,

3
hw/rtl/cache/VX_cache.v vendored
View file

@ -33,8 +33,6 @@ module VX_cache #(
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 0,
@ -335,7 +333,6 @@ module VX_cache #(
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE),