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minor update

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This commit is contained in:
Blaise Tine 2021-04-16 02:45:37 -07:00
parent 90a9325d6d
commit f4c52a41fa
8 changed files with 1294 additions and 890 deletions
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1
driver/tests/tex_demo/common.h
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@ -9,6 +9,7 @@ struct kernel_arg_t {
uint8_t filter;
uint8_t wrap;
uint8_t use_sw;
uint32_t lod;
uint8_t src_logWidth;
uint8_t src_logHeight;
uint8_t src_stride;

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driver/tests/tex_demo/kernel.bin
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6
driver/tests/tex_demo/kernel.c
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@ -30,10 +30,10 @@ void kernel_body(int task_id, void* arg) {
int32_t v = (int32_t)(fv * (1<<20));
#ifdef ENABLE_SW
if (state->use_sw) {
dst_row[x] = tex_sw(state, 0, u, v, 0x0);
dst_row[x] = (state->filter == 2) ? tex3_sw(state, 0, u, v, state->lod) : tex_sw(state, 0, u, v, state->lod);
} else {
#endif
dst_row[x] = vx_tex(0, u, v, 0x0);
dst_row[x] = (state->filter == 2) ? vx_tex3(0, u, v, state->lod) : vx_tex(0, u, v, state->lod);
#ifdef ENABLE_SW
}
#endif
@ -54,7 +54,7 @@ int main() {
vx_csr_write(CSR_TEX_HEIGHT(0), arg->src_logHeight);
vx_csr_write(CSR_TEX_FORMAT(0), arg->format);
vx_csr_write(CSR_TEX_WRAP(0), (arg->wrap << 2) | arg->wrap);
vx_csr_write(CSR_TEX_FILTER(0), arg->filter);
vx_csr_write(CSR_TEX_FILTER(0), (arg->filter ? 1 : 0));
struct tile_arg_t targ;
targ.state = arg;

2163
driver/tests/tex_demo/kernel.dump
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driver/tests/tex_demo/kernel.elf
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1
driver/tests/tex_demo/main.cpp
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@ -207,6 +207,7 @@ int main(int argc, char *argv[]) {
kernel_arg.filter = filter;
kernel_arg.wrap = wrap;
kernel_arg.use_sw = use_sw;
kernel_arg.lod = 0x0;
kernel_arg.src_logWidth = (uint32_t)std::log2(src_width);
kernel_arg.src_logHeight = (uint32_t)std::log2(src_height);

11
driver/tests/tex_demo/texsw.h
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@ -135,10 +135,10 @@ inline int tex_sw(struct kernel_arg_t* state, int stage, int u, int v, int lod)
inline int vx_tex3(int stage, int u, int v, int lod) {
int lodn = MIN(lod + 0x100000, TEX_LOD_MAX);
int a = vx_tex(0, u, v, lod);
int b = vx_tex(0, u, v, lodn);
int a = vx_tex(0, u, v, lod);
int b = vx_tex(0, u, v, lodn);
int al = a & 0x00ff00ff;
int ah = (a >> 8) & 0x00ff00ff;
int ah = (a >> 8) & 0x00ff00ff;
int bl = b & 0x00ff00ff;
int bh = (b >> 8) & 0x00ff00ff;
int frac = (lod >> 12) & 0xff;
@ -150,13 +150,14 @@ inline int vx_tex3(int stage, int u, int v, int lod) {
inline int tex3_sw(struct kernel_arg_t* state, int stage, int u, int v, int lod) {
int lodn = MIN(lod + 0x10000, TEX_LOD_MAX);
int a = tex_sw(state, 0, u, v, lod);
int a = tex_sw(state, 0, u, v, lod);
int b = tex_sw(state, 0, u, v, lodn);
int al = a & 0x00ff00ff;
int ah = (a >> 8) & 0x00ff00ff;
int bl = b & 0x00ff00ff;
int bh = (b >> 8) & 0x00ff00ff;
int frac = lod & 0xffff;
int frac = (lod >> 12) & 0xff;
int cl = (al + (((bl - al) * frac) >> 8)) & 0x00ff00ff;
int ch = (ah + (((bh - ah) * frac) >> 8)) & 0x00ff00ff;
int c = al | (ah << 8);

2
hw/rtl/VX_config.vh
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@ -295,7 +295,7 @@
// Size of cache in bytes
`ifndef DCACHE_SIZE
`define DCACHE_SIZE 16384
`define DCACHE_SIZE 65536
`endif
// Number of banks