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operands optimization
This commit is contained in:
Blaise Tine
parent
0468577b0b
commit
f506ae6cea
2 changed files with 79 additions and 115 deletions
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@ -46,6 +46,8 @@ module VX_operands import VX_gpu_pkg::*; #(
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reg [`NUM_THREADS-1:0] cache_tmask_n [ISSUE_RATIO-1:0];
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reg [ISSUE_RATIO-1:0] cache_eop, cache_eop_n;
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reg valid_out_r;
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reg [DATAW-1:0] data_out_r;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data, rs3_data_n;
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@ -57,11 +59,11 @@ module VX_operands import VX_gpu_pkg::*; #(
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reg rs3_ready, rs3_ready_n;
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reg data_ready, data_ready_n;
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wire ready_out = operands_if[i].ready;
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wire is_rs1_zero = (scoreboard_if[i].data.rs1 == 0);
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wire is_rs2_zero = (scoreboard_if[i].data.rs2 == 0);
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wire is_rs3_zero = (scoreboard_if[i].data.rs3 == 0);
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VX_operands_if staging_if();
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wire is_rs3_zero = (scoreboard_if[i].data.rs3 == 0);
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always @(*) begin
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state_n = state;
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@ -82,7 +84,7 @@ module VX_operands import VX_gpu_pkg::*; #(
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case (state)
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STATE_IDLE: begin
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if (staging_if.valid && staging_if.ready) begin
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if (valid_out_r && ready_out) begin
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data_ready_n = 0;
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end
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if (scoreboard_if[i].valid && data_ready_n == 0) begin
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@ -170,31 +172,70 @@ module VX_operands import VX_gpu_pkg::*; #(
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end
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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state <= STATE_IDLE;
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gpr_rd_rid <= '0;
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gpr_rd_wis <= '0;
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cache_eop <= {ISSUE_RATIO{1'b1}};
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cache_eop <= {ISSUE_RATIO{1'b1}};
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data_ready <= 0;
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valid_out_r <= 0;
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end else begin
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state <= state_n;
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rs2 <= rs2_n;
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rs3 <= rs3_n;
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rs2_ready <= rs2_ready_n;
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rs3_ready <= rs3_ready_n;
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rs1_data <= rs1_data_n;
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rs2_data <= rs2_data_n;
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rs3_data <= rs3_data_n;
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gpr_rd_rid <= gpr_rd_rid_n;
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gpr_rd_wis <= gpr_rd_wis_n;
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cache_data <= cache_data_n;
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cache_reg <= cache_reg_n;
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cache_tmask <= cache_tmask_n;
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cache_eop <= cache_eop_n;
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data_ready <= data_ready_n;
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data_ready <= data_ready_n;
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if (~valid_out_r) begin
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valid_out_r <= scoreboard_if[i].valid && data_ready;
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end else if (ready_out) begin
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valid_out_r <= 0;
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end
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end
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end
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if (~valid_out_r) begin
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data_out_r <= {scoreboard_if[i].data.uuid,
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scoreboard_if[i].data.wis,
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scoreboard_if[i].data.tmask,
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scoreboard_if[i].data.PC,
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scoreboard_if[i].data.wb,
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scoreboard_if[i].data.ex_type,
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scoreboard_if[i].data.op_type,
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scoreboard_if[i].data.op_mod,
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scoreboard_if[i].data.use_PC,
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scoreboard_if[i].data.use_imm,
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scoreboard_if[i].data.imm,
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scoreboard_if[i].data.rd};
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end
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gpr_rd_rid <= gpr_rd_rid_n;
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gpr_rd_wis <= gpr_rd_wis_n;
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rs2_ready <= rs2_ready_n;
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rs3_ready <= rs3_ready_n;
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rs2 <= rs2_n;
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rs3 <= rs3_n;
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rs1_data <= rs1_data_n;
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rs2_data <= rs2_data_n;
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rs3_data <= rs3_data_n;
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cache_data <= cache_data_n;
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cache_reg <= cache_reg_n;
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cache_tmask <= cache_tmask_n;
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end
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assign operands_if[i].valid = valid_out_r;
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assign {operands_if[i].data.uuid,
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operands_if[i].data.wis,
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operands_if[i].data.tmask,
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operands_if[i].data.PC,
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operands_if[i].data.wb,
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operands_if[i].data.ex_type,
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operands_if[i].data.op_type,
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operands_if[i].data.op_mod,
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operands_if[i].data.use_PC,
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operands_if[i].data.use_imm,
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operands_if[i].data.imm,
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operands_if[i].data.rd} = data_out_r;
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assign operands_if[i].data.rs1_data = rs1_data;
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assign operands_if[i].data.rs2_data = rs2_data;
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assign operands_if[i].data.rs3_data = rs3_data;
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assign scoreboard_if[i].ready = ~valid_out_r && data_ready;
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// GPR banks
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`ifdef GPR_RESET
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@ -228,74 +269,6 @@ module VX_operands import VX_gpu_pkg::*; #(
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.rdata (gpr_rd_data[j])
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);
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end
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// staging buffer
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`RESET_RELAY (stg_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW)
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) stg_buf (
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.clk (clk),
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.reset (stg_buf_reset),
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.valid_in (scoreboard_if[i].valid),
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.ready_in (scoreboard_if[i].ready),
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.data_in ({
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scoreboard_if[i].data.uuid,
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scoreboard_if[i].data.wis,
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scoreboard_if[i].data.tmask,
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scoreboard_if[i].data.PC,
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scoreboard_if[i].data.wb,
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scoreboard_if[i].data.ex_type,
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scoreboard_if[i].data.op_type,
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scoreboard_if[i].data.op_mod,
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scoreboard_if[i].data.use_PC,
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scoreboard_if[i].data.use_imm,
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scoreboard_if[i].data.imm,
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scoreboard_if[i].data.rd}),
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.data_out ({
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staging_if.data.uuid,
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staging_if.data.wis,
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staging_if.data.tmask,
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staging_if.data.PC,
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staging_if.data.wb,
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staging_if.data.ex_type,
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staging_if.data.op_type,
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staging_if.data.op_mod,
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staging_if.data.use_PC,
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staging_if.data.use_imm,
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staging_if.data.imm,
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staging_if.data.rd}),
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.valid_out (staging_if.valid),
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.ready_out (staging_if.ready)
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);
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assign staging_if.data.rs1_data = rs1_data;
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assign staging_if.data.rs2_data = rs2_data;
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assign staging_if.data.rs3_data = rs3_data;
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// output buffer
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wire valid_stg, ready_stg;
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assign valid_stg = staging_if.valid && data_ready;
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assign staging_if.ready = ready_stg && data_ready;
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`RESET_RELAY (out_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW + (3 * `NUM_THREADS * `XLEN)),
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.SIZE (2),
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.OUT_REG (2)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_stg),
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.ready_in (ready_stg),
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.data_in (staging_if.data),
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.data_out (operands_if[i].data),
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.valid_out (operands_if[i].valid),
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.ready_out (operands_if[i].ready)
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);
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end
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endmodule
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@ -51,7 +51,6 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0] inuse_regs;
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VX_ibuffer_if staging_if();
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wire writeback_fire = writeback_if[i].valid && writeback_if[i].data.eop;
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@ -84,10 +83,17 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
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reg [DATAW-1:0] data_out_r;
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reg valid_out_r;
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wire ready_out;
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wire [3:0] ready_masks = ~{inuse_rd, inuse_rs1, inuse_rs2, inuse_rs3};
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wire deps_ready = (& ready_masks);
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wire valid_in = ibuffer_if[i].valid && deps_ready;
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wire ready_in = ~valid_out_r && deps_ready;
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wire [DATAW-1:0] data_in = ibuffer_if[i].data;
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assign ready_out = scoreboard_if[i].ready;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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@ -97,40 +103,25 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
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inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] <= 0;
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end
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if (~valid_out_r) begin
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valid_out_r <= ibuffer_if[i].valid && deps_ready;
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end else if (staging_if.ready) begin
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if (staging_if.data.wb) begin
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inuse_regs[staging_if.data.wis][staging_if.data.rd] <= 1;
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valid_out_r <= valid_in;
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end else if (ready_out) begin
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if (scoreboard_if[i].data.wb) begin
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inuse_regs[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= 1;
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`ifdef PERF_ENABLE
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inuse_units[staging_if.data.wis][staging_if.data.rd] <= staging_if.data.ex_type;
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inuse_units[scoreboard_if[i].data.wis][scoreboard_if[i].data.rd] <= scoreboard_if[i].data.ex_type;
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`endif
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end
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valid_out_r <= 0;
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end
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end
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if (~valid_out_r) begin
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data_out_r <= ibuffer_if[i].data;
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data_out_r <= data_in;
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end
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end
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assign ibuffer_if[i].ready = ~valid_out_r && deps_ready;
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assign staging_if.valid = valid_out_r;
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assign staging_if.data = data_out_r;
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (0),
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.OUT_REG (2)
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) out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (staging_if.valid),
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.ready_in (staging_if.ready),
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.data_in (staging_if.data),
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.data_out (scoreboard_if[i].data),
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.valid_out (scoreboard_if[i].valid),
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.ready_out (scoreboard_if[i].ready)
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);
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assign ibuffer_if[i].ready = ready_in;
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assign scoreboard_if[i].valid = valid_out_r;
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assign scoreboard_if[i].data = data_out_r;
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`ifdef SIMULATION
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reg [31:0] timeout_ctr;
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