mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
Merge branch 'harmonica-iset' of https://github.com/cdkersey/harptool into harmonica-iset
This commit is contained in:
chad
commit
f544ca1e49
8 changed files with 158 additions and 59 deletions
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@ -132,7 +132,8 @@ The bit fields in the instruction encodings depend heavily on this quality.
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30 "skep" 1REG 31 "reti" NONE 32 "tlbrm" 1REG
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33 "itof" 2REG 34 "ftoi" 2REG 35 "fadd" 3REG
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36 "fsub" 3REG 37 "fmul" 3REG 38 "fdiv" 3REG
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39 "fneg" 2REG
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39 "fneg" 2REG 3a "wspawn" 2REG 3b "split" NONE
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3c "join" NONE
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\end{verbatim}
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\subsection{Word Encoding}
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@ -346,6 +347,8 @@ format, which can be fixed point or floating point.
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\texttt{jalis} \%link, \%n, \textsc{\#RelDest}&Jump and link immediate, spawning N active lanes.\\
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\texttt{jalrs} \%link, \%n, \%dest&Jump and link indirect, spawning N active lanes.\\
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\texttt{jmprt} \%addr&Jump indirect, terminating execution on all but a single lane.\\
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\texttt{split}&Control flow diverge.\\
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\texttt{join}&Control flow reconverge.\\
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\end{tabular}
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\end{center}
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@ -412,6 +415,14 @@ The current response to this is to trap to the operating system (interrupt numbe
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The \texttt{clone}, \texttt{jalis}, \texttt{jalrs}, and \texttt{jmprt} instructions form the basis of SIMD context control in the HARP instruction set.
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Context is created using \texttt{clone}, the waiting threads are spawned using \texttt{jalrs} or \texttt{jalis}, ``jump-and-link immediate/register and spawn'', and finally the parallel section returns using \texttt{jmprt}, ``jump register and terminate'', best thought of as ``return and terminate.''
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There are times when a control flow operation will need to be predicated, going one direction on some lanes and the other direction on other lanes.
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For this, the HARP instruction set provides the \texttt{split} and \texttt{join} instructions.
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When a predicated \texttt{split} is first encountered, only the lanes for which the \texttt{split}'s predicate are true are allowed to continue.
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The other lanes are masked out until the corresponding \texttt{join} is encountered.
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The first time \texttt{join} is reached, control flow returns to the instruction following the corresponding \texttt{split} with the set of masked-out lanes complemented.
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The second time the same \texttt{join} is reached, control flow falls through and the original lane mask is restored.
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A hardware stack is maintained to keep track of nested \texttt{split}s.
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\section{Default I/O Devices}
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The emulator currently only supports a single I/O device, simple console I/O.
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Writing to the address \texttt{0x800...0} (an address with its MSB set and all other bits cleared) causes text to be written to the display.
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@ -8,7 +8,7 @@ PREFIX ?= /usr/local
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LIB_OBJS=args.o obj.o mem.o core.o instruction.o enc.o util.o lex.yy.o
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all: harptool libharplib.so libharplib.a libqsim-harp.so
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all: harptool libharplib.so libharplib.a # libqsim-harp.so
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# Use -static so we don't have to install the library in order to just run
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# Harptool.
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@ -46,6 +46,8 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id) :
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for (Word i = 0; i < a.getNPRegs(); ++i) {
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pred[j].push_back(Reg<bool>(id, regNum++));
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}
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tmask.push_back(true);
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}
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/* Set initial register contents. */
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@ -131,6 +133,11 @@ void Core::step() {
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D_RAW(" (");
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for (unsigned i = 0; i < shadowPReg.size(); ++i) D_RAW(shadowPReg[i]);
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D_RAW(')' << endl);
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D(3, "Thread mask:");
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D_RAW(" ");
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for (unsigned i = 0; i < tmask.size(); ++i) D_RAW(tmask[i] << ' ');
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D_RAW(endl);
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}
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#endif
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@ -6,6 +6,7 @@
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#include <string>
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#include <vector>
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#include <stack>
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#include "types.h"
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#include "archdef.h"
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@ -26,7 +27,7 @@ namespace Harp {
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Reg &operator=(T r) { val = r; doWrite(); return *this; }
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operator T() { doRead(); return val; }
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operator T() const { doRead(); return val; }
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void trunc(Size s) {
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Word mask((~0ull >> (sizeof(Word)-s)*8));
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@ -39,14 +40,36 @@ namespace Harp {
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#ifdef EMU_INSTRUMENTATION
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/* Access size here is 8, representing the register size of 64-bit cores. */
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void doWrite() { reg_doWrite(cpuId, regNum); }
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void doRead() { reg_doRead(cpuId, regNum); }
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void doWrite() const { reg_doWrite(cpuId, regNum); }
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void doRead() const { reg_doRead(cpuId, regNum); }
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#else
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void doWrite() {}
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void doRead() {}
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void doWrite() const {}
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void doRead() const {}
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#endif
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};
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// Entry in the IPDOM Stack
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struct DomStackEntry {
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DomStackEntry(
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unsigned p, const std::vector<std::vector<Reg<bool> > >& m, Word pc
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): pc(pc), fallThrough(false)
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{
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std::cout << "New DomStackEntry:";
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for (unsigned i = 0; i < m.size(); ++i) {
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tmask.push_back(!bool(m[i][p]));
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std::cout << ' ' << bool(m[i][p]);
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}
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std::cout << std::endl;
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}
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DomStackEntry(const std::vector<bool> &tmask):
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tmask(tmask), fallThrough(true) {}
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bool fallThrough;
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std::vector<bool> tmask;
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Word pc;
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};
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class Core {
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public:
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Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id=0);
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@ -67,6 +90,9 @@ namespace Harp {
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std::vector<std::vector<Reg<Word> > > reg;
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std::vector<std::vector<Reg<bool> > > pred;
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std::vector<bool> tmask;
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std::stack<DomStackEntry> domStack;
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std::vector<Word> shadowReg;
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std::vector<bool> shadowPReg;
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@ -30,7 +30,8 @@ namespace Harp {
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JALI, JALR, JMPI, JMPR, CLONE, JALIS, JALRS,
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JMPRT, LD, ST, LDI, RTOP, ANDP, ORP, XORP, NOTP, ISNEG,
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ISZERO, HALT, TRAP, JMPRU, SKEP, RETI, TLBRM,
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ITOF, FTOI, FADD, FSUB, FMUL, FDIV, FNEG, WSPAWN };
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ITOF, FTOI, FADD, FSUB, FMUL, FDIV, FNEG, WSPAWN,
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SPLIT, JOIN };
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enum ArgClass {
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AC_NONE, AC_2REG, AC_2IMM, AC_3REG, AC_3PREG, AC_3IMM, AC_3REGSRC,
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AC_1IMM, AC_1REG, AC_3IMMSRC, AC_PREG_REG, AC_2PREG, AC_2REGSRC
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@ -81,6 +81,8 @@ Instruction::InstTableEntry Instruction::instTable[] = {
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{"fdiv", false, false, false, false, AC_3REG, ITYPE_FPDIV },
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{"fneg", false, false, false, false, AC_2REG, ITYPE_FPBASIC },
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{"wspawn", false, false, true, false, AC_2REGSRC, ITYPE_NULL },
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{"split", false, false, true, false, AC_NONE, ITYPE_NULL },
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{"join", false, false, true, false, AC_NONE, ITYPE_NULL },
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{NULL,false,false,false,false,AC_NONE,ITYPE_NULL}/////// End of table.
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};
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@ -119,12 +121,16 @@ void Instruction::executeOn(Core &c) {
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return;
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}
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/* Also throw exceptions on divergent branches. */
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if (predicated && instTable[op].controlFlow) {
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bool p0 = c.pred[0][pred];
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for (Size t = 1; t < c.activeThreads; t++) {
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if (c.pred[t][pred] != p0) throw DivergentBranchException();
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/* Also throw exceptions on non-masked divergent branches. */
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if (instTable[op].controlFlow) {
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Size t, count, active;
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for (t = 0, count = 0, active = 0; t < c.activeThreads; ++t) {
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if ((!predicated || c.pred[t][pred]) && c.tmask[t]) ++count;
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if (c.tmask[t]) ++active;
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}
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if (count != 0 && count != active)
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throw DivergentBranchException();
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}
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Size nextActiveThreads = c.activeThreads;
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@ -133,8 +139,12 @@ void Instruction::executeOn(Core &c) {
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for (Size t = 0; t < c.activeThreads; t++) {
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vector<Reg<Word> > ®(c.reg[t]);
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vector<Reg<bool> > &pReg(c.pred[t]);
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stack<DomStackEntry> &domStack(c.domStack);
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if (predicated && !pReg[pred]) continue;
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// If this thread is masked out, don't execute the instruction, unless it's
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// a split or join.
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if (((predicated && !pReg[pred]) || !c.tmask[t]) &&
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op != SPLIT && op != JOIN) continue;
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Word memAddr;
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switch (op) {
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@ -288,6 +298,23 @@ void Instruction::executeOn(Core &c) {
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case FDIV: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) /
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double(Float(reg[rsrc[1]], wordSz)),wordSz);
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break;
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case SPLIT:if (t == 0) {
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// TODO: if mask becomes all-zero, fall through
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DomStackEntry e(pred, c.pred, c.pc);
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c.domStack.push(c.tmask);
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c.domStack.push(e);
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for (unsigned i = 0; i < e.tmask.size(); ++i)
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c.tmask[i] = !e.tmask[i];
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}
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break;
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case JOIN: if (t == 0) {
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// TODO: if mask becomes all-zero, fall through
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if (!c.domStack.top().fallThrough)
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c.pc = c.domStack.top().pc;
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c.tmask = c.domStack.top().tmask;
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c.domStack.pop();
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}
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break;
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default:
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cout << "ERROR: Unsupported instruction: " << *this << "\n";
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exit(1);
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@ -5,12 +5,14 @@ HARPDIS = ../harptool -D
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4BARCH = 4b16/16/2
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all: simple.bin sieve.bin 2thread.bin simple.4b.bin sieve.4b.bin 2thread.4b.bin bubble.bin bubble.4b.bin dotprod.bin dotprod.4b.bin matmul.bin matmul.4b.bin \
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matmul-mt.s
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matmul-mt.bin diverge.bin
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run: simple.out sieve.out 2thread.out simple.4b.out sieve.4b.out 2thread.4b.out bubble.out bubble.4b.out dotprod.out dotprod.4b.out matmul.out matmul.4b.out\
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matmul-mt.out
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matmul-mt.out diverge.out
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disas: simple.d sieve.d 2thread.d simple.4b.d sieve.4b.d 2thread.4b.d bubble.d bubble.4b.d dotprod.d dotprod.4b.d matmul.d matmul.4b.d matmul-mt.d
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disas: simple.d sieve.d 2thread.d simple.4b.d sieve.4b.d 2thread.4b.d bubble.d \
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bubble.4b.d dotprod.d dotprod.4b.d matmul.d matmul.4b.d matmul-mt.d \
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diverge.d diverge.4b.d
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%.4b.out : %.4b.bin
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$(HARPEM) -a $(4BARCH) -c $< > $@
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@ -18,50 +20,11 @@ disas: simple.d sieve.d 2thread.d simple.4b.d sieve.4b.d 2thread.4b.d bubble.d b
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%.out : %.bin
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$(HARPEM) -c $< > $@
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2thread.bin : boot.HOF lib.HOF 2thread.HOF
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$(HARPLD) -o 2thread.bin $^
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2thread.4b.bin : boot.4b.HOF lib.4b.HOF 2thread.4b.HOF
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$(HARPLD) --arch $(4BARCH) -o 2thread.4b.bin $^
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bubble.bin : boot.HOF lib.HOF bubble.HOF
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$(HARPLD) -o bubble.bin $^
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bubble.4b.bin : boot.4b.HOF lib.4b.HOF bubble.4b.HOF
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$(HARPLD) --arch $(4BARCH) -o bubble.4b.bin $^
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simple.bin : boot.HOF lib.HOF simple.HOF
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$(HARPLD) -o $@ $^
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sieve.bin : boot.HOF lib.HOF sieve.HOF
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$(HARPLD) -o $@ $^
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dotprod.bin : boot.HOF lib.HOF dotprod.HOF
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$(HARPLD) -o $@ $^
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matmul.bin : boot.HOF lib.HOF matmul.HOF
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$(HARPLD) -o $@ $^
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matmul-mt.bin : boot.HOF lib.HOF matmul-mt.HOF
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$(HARPLD) -o $@ $^
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simple.4b.bin : boot.4b.HOF lib.4b.HOF simple.4b.HOF
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%.4b.bin : boot.4b.HOF lib.4b.HOF %.4b.HOF
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$(HARPLD) --arch $(4BARCH) -o $@ $^
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sieve.4b.bin : boot.4b.HOF lib.4b.HOF sieve.4b.HOF
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$(HARPLD) --arch $(4BARCH) -o $@ $^
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dotprod.4b.bin : boot.4b.HOF lib.4b.HOF dotprod.4b.HOF
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$(HARPLD) --arch $(4BARCH) -o $@ $^
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matmul.4b.bin : boot.4b.HOF lib.4b.HOF matmul.4b.HOF
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$(HARPLD) --arch $(4BARCH) -o $@ $^
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%.4b.bin : %.4b.HOF
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$(HARPLD) --arch $(4BARCH) -o $@ $<
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%.bin : %.HOF
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$(HARPLD) -o $@ $<
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%.bin : boot.HOF lib.HOF %.HOF
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$(HARPLD) -o $@ $^
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%.4b.HOF : %.s
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$(HARPAS) --arch $(4BARCH) -o $@ $<
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64
src/test/diverge.s
Normal file
64
src/test/diverge.s
Normal file
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@ -0,0 +1,64 @@
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/*******************************************************************************
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Harptools by Chad D. Kersey, Summer 2011
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********************************************************************************
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Sample HARP assmebly program.
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*******************************************************************************/
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/* Divergent branch: test immediate postdominator branch divergence support. */
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.def THREADS 8
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.align 4096
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.perm x
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.entry
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.global
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entry:
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ldi %r0, #1
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ldi %r1, THREADS
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sloop: clone %r0
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addi %r0, %r0, #1
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sub %r2, %r1, %r0
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rtop @p0, %r2
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@p0 ? jmpi sloop
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ldi %r0, #0
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jalis %r5, %r1, dthread;
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ldi %r0, #0
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ldi %r1, (__WORD * THREADS)
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ploop: ld %r7, %r0, array
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jali %r5, printdec
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addi %r0, %r0, __WORD
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sub %r7, %r1, %r0
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rtop @p0, %r7
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@p0 ? jmpi ploop
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trap;
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dthread: ldi %r1, #10
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ldi %r2, #0
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loop: andi %r3, %r0, #1
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rtop @p1, %r3
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@p1 ? split
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@p1 ? jmpi else
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add %r2, %r2, %r0
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jmpi after
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else: sub %r2, %r2, %r0
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after: join
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subi %r1, %r1, #1
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rtop @p0, %r1
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@p0 ? jmpi loop
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shli %r4, %r0, (`__WORD)
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st %r2, %r4, array
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jmprt %r5;
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.align 4096
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array: .space 4096
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Loading…
Add table
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Reference in a new issue