chipscope update

hw/afu/xrt/vortex_afu.v

@@ -46,7 +46,11 @@
 module vortex_afu #(
 	parameter C_S_AXI_CONTROL_ADDR_WIDTH = 6,
 	parameter C_S_AXI_CONTROL_DATA_WIDTH = 32,
+`ifdef CHIPSCOPE
+	parameter C_M_AXI_GMEM_ID_WIDTH      = 32,
+`else
 	parameter C_M_AXI_GMEM_ID_WIDTH      = 16,
+`endif
 	parameter C_M_AXI_GMEM_ADDR_WIDTH    = 32,
 	parameter C_M_AXI_GMEM_DATA_WIDTH    = `VX_MEM_DATA_WIDTH
 ) (
@@ -294,6 +298,78 @@ module vortex_afu #(
 	assign m_axi_mem_awaddr = m_axi_mem_awaddr_r;
 	assign m_axi_mem_araddr = m_axi_mem_araddr_r;
 
+`ifdef CHIPSCOPE
+    ila_afu ila_afu_inst (
+        .clk    (ap_clk),
+        .probe0 ({m_axi_mem_awvalid,
+				m_axi_mem_awready,
+				m_axi_mem_awaddr,
+				m_axi_mem_awid,
+				m_axi_mem_awlen,
+				m_axi_mem_awsize,
+				m_axi_mem_awburst,
+				m_axi_mem_awlock,
+				m_axi_mem_awcache,
+				m_axi_mem_awprot,
+				m_axi_mem_awqos,
+				m_axi_mem_awregion}),
+        .probe1 ({m_axi_mem_wvalid,
+				m_axi_mem_wready,
+				m_axi_mem_wdata,
+				m_axi_mem_wstrb,
+				m_axi_mem_wlast}),
+        .probe2 ({m_axi_mem_arvalid,
+				m_axi_mem_arready,
+				m_axi_mem_araddr,
+				m_axi_mem_arid,
+				m_axi_mem_arlen,
+				m_axi_mem_arsize,
+				m_axi_mem_arburst,
+				m_axi_mem_arlock,
+				m_axi_mem_arcache,
+				m_axi_mem_arprot,
+				m_axi_mem_arqos,
+				m_axi_mem_arregion}),
+        .probe3 ({m_axi_mem_rvalid,
+				m_axi_mem_rready,
+				m_axi_mem_rdata,
+				m_axi_mem_rlast,
+				m_axi_mem_rid,
+				m_axi_mem_rresp}),
+        .probe4 ({m_axi_mem_bvalid,
+				m_axi_mem_bready,
+				m_axi_mem_bresp,
+				m_axi_mem_bid}),
+		.probe5 ({s_axi_ctrl_awvalid,
+				s_axi_ctrl_awready,
+				s_axi_ctrl_awaddr,
+				s_axi_ctrl_wvalid,
+				s_axi_ctrl_wready,
+				s_axi_ctrl_wdata,
+				s_axi_ctrl_wstrb,
+				s_axi_ctrl_arvalid,
+				s_axi_ctrl_arready,
+				s_axi_ctrl_araddr,
+				s_axi_ctrl_rvalid,
+				s_axi_ctrl_rready,
+				s_axi_ctrl_rdata,
+				s_axi_ctrl_rresp,
+				s_axi_ctrl_bvalid,
+				s_axi_ctrl_bready,
+				s_axi_ctrl_bresp}),
+		.probe6 ({ap_start,
+                ap_done,
+				ap_ready,
+				ap_idle,
+				interrupt}),
+		.probe7 ({vx_reset, 
+				vx_busy,
+				dcr_wr_valid, 
+				dcr_wr_addr, 
+				dcr_wr_data})
+    );
+`endif
+
 `ifdef SIMULATION
 `ifndef VERILATOR
 	// disable assertions until full reset

hw/rtl/VX_define.vh

@@ -35,6 +35,8 @@
 
 `ifdef SIMULATION
 `define UUID_BITS       44
+`elsif CHIPSCOPE 
+`define UUID_BITS       16
 `else
 `define UUID_BITS       0
 `endif

hw/rtl/VX_issue.sv

@@ -155,6 +155,14 @@ module VX_issue #(
                         $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.tmask, ibuffer_if.rd, ibuffer_if.wb, 
                         in_use_regs[0], in_use_regs[1], in_use_regs[2], in_use_regs[3], ~dispatch_if.ready, ibuffer_if.uuid));
 
+`ifdef CHIPSCOPE
+    ila_issue ila_issue_inst (
+        .clk    (clk),
+        .probe0 ({dispatch_if.valid, dispatch_if.ready, dispatch_if.PC, dispatch_if.tmask, dispatch_if.wid, dispatch_if.ex_type, dispatch_if.op_type, dispatch_if.uuid}),
+        .probe1 ({writeback_if.valid, writeback_if.PC, writeback_if.tmask, writeback_if.wid, writeback_if.uuid})
+    );
+`endif
+
     `SCOPE_ASSIGN (issue_fire,        ibuffer_if.valid && ibuffer_if.ready);
     `SCOPE_ASSIGN (issue_uuid,        ibuffer_if.uuid);
     `SCOPE_ASSIGN (issue_tmask,       ibuffer_if.tmask);

hw/rtl/VX_platform.vh

@@ -81,16 +81,24 @@
         if (!(cond)) $error msg; \
     endgenerate
 
-`define ERROR(msg) \
-    $error msg
+`ifdef SIMULATION
+    `define ERROR(msg) \
+        $error msg
+
+    `define ASSERT(cond, msg) \
+        assert(cond) else $error msg
+
+    `define RUNTIME_ASSERT(cond, msg)     \
+        always @(posedge clk) begin       \
+            assert(cond) else $error msg; \
+        end
+`else
+    `define ERROR(msg)                  //
+    `define ASSERT(cond, msg)           //
+    `define RUNTIME_ASSERT(cond, msg)
+`endif
 
-`define ASSERT(cond, msg) \
-    assert(cond) else $error msg
 
-`define RUNTIME_ASSERT(cond, msg)     \
-    always @(posedge clk) begin       \
-        assert(cond) else $error msg; \
-    end
 
 ///////////////////////////////////////////////////////////////////////////////
 
@@ -98,23 +106,19 @@
 `define USE_FAST_BRAM   (* ramstyle = "MLAB, no_rw_check" *)
 `define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
 `define DISABLE_BRAM    (* ramstyle = "logic" *)
-`define PRESERVE_REG    (* preserve *)
+`define PRESERVE_NET    (* preserve *)
 `define STRING_TYPE     string
 `elsif VIVADO
-//`define USE_FAST_BRAM   (* ram_style = "distributed" *)
-//`define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *)
-//`define DISABLE_BRAM    (* ram_style = "registers" *)
-//`define PRESERVE_REG    (* keep = "true" *)
-`define USE_FAST_BRAM
-`define NO_RW_RAM_CHECK
-`define DISABLE_BRAM
-`define PRESERVE_REG
+`define USE_FAST_BRAM   (* ram_style = "distributed" *)
+`define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *)
+`define DISABLE_BRAM    (* ram_style = "registers" *)
+`define PRESERVE_NET    (* keep = "true" *)
 `define STRING_TYPE
 `else
 `define USE_FAST_BRAM
 `define NO_RW_RAM_CHECK
 `define DISABLE_BRAM
-`define PRESERVE_REG
+`define PRESERVE_NET
 `define STRING_TYPE     string
 `endif
 

hw/rtl/VX_warp_sched.sv

@@ -57,7 +57,7 @@ module VX_warp_sched #(
     wire                    schedule_ready;
     wire                    warp_scheduled;
 
-    reg [`PERF_CTR_BITS-1:0]    cycles;
+    reg [`PERF_CTR_BITS-1:0] cycles;
 
     reg [`NUM_WARPS-1:0][UUID_WIDTH-1:0] issued_instrs;
     wire [UUID_WIDTH-1:0] instr_uuid;

hw/rtl/Vortex.sv

@@ -48,16 +48,6 @@ module Vortex (
     output wire                             busy
 );
 
-`ifdef CHIPSCOPE
-    // ILA monitoring combinatorial adder
-    ila_0 i_ila_0 (
-        .clk    (ap_clk),              
-        .probe0 (mem_req_valid && mem_req_ready),
-        .probe1 (mem_rsp_valid && mem_rsp_ready),
-        .probe2 (dcr_wr_valid)
-    );
-`endif
-
 `ifdef PERF_ENABLE
     VX_perf_memsys_if perf_memsys_if[`NUM_CLUSTERS]();
     VX_perf_memsys_if perf_memsys_total_if();    

hw/rtl/fpu_unit/VX_fpu_define.vh

@@ -12,4 +12,5 @@
 `IGNORE_WARNINGS_BEGIN
 import VX_fpu_types::*;
 `IGNORE_WARNINGS_END
+
 `endif

hw/rtl/libs/VX_reset_relay.sv

@@ -12,7 +12,7 @@ module VX_reset_relay #(
     if (MAX_FANOUT >= 0 && N > MAX_FANOUT) begin
         localparam F = `UP(MAX_FANOUT);
         localparam R = N / F;
-        `PRESERVE_REG reg [R-1:0] reset_r;
+        `PRESERVE_NET reg [R-1:0] reset_r;
         always @(posedge clk) begin
             reset_r <= {R{reset}};
         end

hw/syn/xilinx/README.md

@@ -6,4 +6,11 @@ make all TARGET=hw PLATFORM=xilinx_u280_xdma_201920_3 PROFILE=1 DEBUG=1 > build_
 
 make all TARGET=hw_emu PLATFORM=xilinx_u280_xdma_201920_3 PROFILE=1 DEBUG=1 > build_hw_emu.log 2>&1
 
-xsim --gui xilinx_u280_xdma_201920_3-0-vortex_afu.wdb &
+xsim --gui xilinx_u280_xdma_201920_3-0-vortex_afu.wdb &
+
+HW synthesis log
+build_xilinx_u280_xdma_201920_3_hw/_x/logs/link/syn/pfm_dynamic_vortex_afu_1_0_synth_1_runme.log
+
+ILA debugging:
+debug_hw --xvc_pcie /dev/xvc_pub.u0 --hw_server
+debug_hw --vivado --host flubber5.crnch.gatech.edu --ltx_file ./build_xilinx_u280_xdma_201920_3_hw/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx

hw/syn/xilinx/tryout/.gitignore

@@ -0,0 +1 @@
+project_1/*

hw/syn/xilinx/tryout/project_1_files/testbench.v

@@ -1,17 +1,21 @@
 `include "VX_define.vh"
 
-`timescale 1ns / 1ps
+`timescale 10ns / 1ns
+
+`define CYCLE_TIME  2
 
 module testbench;
-    // Inpput signals
     reg clk;
     reg resetn;
+    reg [63:0] cycles;
+
     reg vx_reset;
     wire vx_busy;
     reg dcr_wr_valid;
     reg [11:0] dcr_wr_addr;
     reg [31:0] dcr_wr_data;
 
+
     design_1_wrapper UUD(
         .clk_100MHz     (clk),
         .resetn         (resetn),
@@ -22,29 +26,48 @@ module testbench;
         .vx_busy        (vx_busy)
     );
 
-    // clock signal creation
-    always begin
-        clk = 1'b0;
-        #1;
-        clk = 1'b1;
-        #1;
-    end
+    always #(`CYCLE_TIME/2) 
+        clk = ~clk;
     
     initial begin
-        #2;
-        resetn          = 1'b0;
-        vx_reset        = 1'b1;
-        dcr_wr_valid    = 1'b0;
-        #2;
-        resetn          = 1'b1;
-        #2;
-        dcr_wr_valid    = 1'b1;
-        dcr_wr_addr     = `DCR_BASE_STARTUP_ADDR;
-        dcr_wr_data     = `STARTUP_ADDR;
-        #2;
-        dcr_wr_valid    = 1'b0;
-        #20;
-        vx_reset        = 1'b0;
+        clk = 1'b0;
+        resetn = 1'b0;
+        #8 resetn = 1'b1;
+    end
+
+    
+    always @(posedge clk) begin
+        if (~resetn) begin
+            cycles <= 0;
+        end else begin
+            cycles <= cycles + 1;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (~resetn) begin
+            vx_reset     <= 1;
+            dcr_wr_valid <= 0;
+            dcr_wr_addr  <= 0;
+            dcr_wr_data  <= 0;
+        end else begin
+            case (cycles)
+            0:  begin
+                dcr_wr_valid <= 1;
+                dcr_wr_addr  <= `DCR_BASE_STARTUP_ADDR;
+                dcr_wr_data  <= `STARTUP_ADDR;                    
+            end
+            2: begin
+                dcr_wr_valid <= 0;
+                dcr_wr_addr  <= 0;
+                dcr_wr_data  <= 0;
+            end
+            `RESET_DELAY: begin
+                vx_reset <= 0;
+            end
+            default:;
+            endcase
+        end
     end
     
     always @(posedge clk) begin

hw/syn/xilinx/xrt/scripts/package_kernel.tcl

@@ -65,10 +65,29 @@ set_property -verbose -name "top" -value ${krnl_name} -objects $obj
 
 if { $chipscope == 1 } {
     # hw debugging
-    create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_0
-    set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] [get_ips ila_0]
-    generate_target {instantiation_template} [get_files ila_0.xci]
-    set_property generate_synth_checkpoint false [get_files ila_0.xci]
+    create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_afu
+    set_property -dict [list CONFIG.C_NUM_OF_PROBES {8} \
+                             CONFIG.C_DATA_DEPTH {8192} \
+                             CONFIG.C_PROBE0_WIDTH {128} \
+                             CONFIG.C_PROBE1_WIDTH {576} \
+                             CONFIG.C_PROBE2_WIDTH {128} \
+                             CONFIG.C_PROBE3_WIDTH {576} \
+                             CONFIG.C_PROBE4_WIDTH {32} \
+                             CONFIG.C_PROBE5_WIDTH {128} \
+                             CONFIG.C_PROBE6_WIDTH {5} \
+                             CONFIG.C_PROBE7_WIDTH {64} \
+                        ] [get_ips ila_afu]
+    generate_target {instantiation_template} [get_files ila_afu.xci]
+    set_property generate_synth_checkpoint false [get_files ila_afu.xci]
+
+    create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_issue
+    set_property -dict [list CONFIG.C_NUM_OF_PROBES {2} \
+                             CONFIG.C_DATA_DEPTH {8192} \
+                             CONFIG.C_PROBE0_WIDTH {92} \
+                             CONFIG.C_PROBE0_WIDTH {92} \
+                        ] [get_ips ila_issue]
+    generate_target {instantiation_template} [get_files ila_issue.xci]
+    set_property generate_synth_checkpoint false [get_files ila_issue.xci]
 }
 
 update_compile_order -fileset sources_1

hw/syn/xilinx/xrt/xrt.ini

@@ -3,7 +3,7 @@ runtime_log=console
 
 [Emulation]
 #debug_mode=gui
-#user_pre_sim_script=/nethome/btine3/dev/vortex-gfx/hw/syn/xilinx/xrt/scripts/xsim.tcl
+#user_pre_sim_script=xsim.tcl
 
 [Debug]
 profile=true

tests/regression/demo/main.cpp

@@ -1,4 +1,5 @@
 #include <iostream>
+#include <limits>
 #include <unistd.h>
 #include <string.h>
 #include <vortex.h>
@@ -62,9 +63,17 @@ void cleanup() {
   }
 }
 
+void wait_for_enter(const std::string &msg) {
+    std::cout << msg << std::endl;
+    std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
+}
+
 int run_test(const kernel_arg_t& kernel_arg,
              uint32_t buf_size, 
              uint32_t num_points) {
+
+  //wait_for_enter("\nPress ENTER to continue after setting up ILA trigger...");
+              
   // start device
   std::cout << "start device" << std::endl;
   RT_CHECK(vx_start(device));