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Merge branch 'gfx' of https://github.gatech.edu/casl/Vortex into graphics

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This commit is contained in:
Blaise Tine 2022-09-01 19:10:13 -04:00
commit f593627ab2
19 changed files with 122 additions and 120 deletions
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6
hw/ip/altera/arria10/VX_acl_fdiv.sv
View file

@ -30,12 +30,10 @@ module VX_acl_fdiv #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
`RESET_RELAY (fdiv_reset, reset);
for (genvar i = 0; i < NUM_LANES; ++i) begin
acl_fdiv fdiv (
.clk (clk),
.areset (fdiv_reset),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

4
hw/ip/altera/arria10/VX_acl_fma.sv
View file

@ -60,11 +60,9 @@ module VX_acl_fma #(
end
end
`RESET_RELAY (fma_reset, reset);
acl_fmadd fmadd (
.clk (clk),
.areset (fma_reset),
.areset (1'b0),
.en (enable),
.a (a),
.b (b),

4
hw/ip/altera/arria10/VX_acl_fsqrt.sv
View file

@ -30,11 +30,9 @@ module VX_acl_fsqrt #(
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
`RESET_RELAY (fsqrt_reset, reset);
acl_fsqrt fsqrt (
.clk (clk),
.areset (fsqrt_reset),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])

6
hw/ip/altera/stratix10/VX_acl_fdiv.sv
View file

@ -30,12 +30,10 @@ module VX_acl_fdiv #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
`RESET_RELAY (fdiv_reset, reset);
for (genvar i = 0; i < NUM_LANES; ++i) begin
acl_fdiv fdiv (
.clk (clk),
.areset (fdiv_reset),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

4
hw/ip/altera/stratix10/VX_acl_fma.sv
View file

@ -60,11 +60,9 @@ module VX_acl_fma #(
end
end
`RESET_RELAY (fma_reset, reset);
acl_fmadd fmadd (
.clk (clk),
.areset (fma_reset),
.areset (1'b0),
.en (enable),
.a (a),
.b (b),

4
hw/ip/altera/stratix10/VX_acl_fsqrt.sv
View file

@ -30,11 +30,9 @@ module VX_acl_fsqrt #(
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
`RESET_RELAY (fsqrt_reset, reset);
acl_fsqrt fsqrt (
.clk (clk),
.areset (fsqrt_reset),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])

2
hw/rtl/VX_alu_unit.sv
View file

@ -203,7 +203,7 @@ module VX_alu_unit #(
.NUM_INPUTS (RSP_ARB_SIZE),
.DATAW (RSP_ARB_DATAW),
.ARBITER ("R"),
.BUFFERED (2)
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (reset),

14
hw/rtl/VX_config.vh
View file

@ -402,7 +402,7 @@
// Core Response Queue Size
`ifndef ICACHE_CRSQ_SIZE
`define ICACHE_CRSQ_SIZE 4
`define ICACHE_CRSQ_SIZE 2
`endif
// Miss Handling Register Size
@ -466,7 +466,7 @@
// Core Response Queue Size
`ifndef DCACHE_CRSQ_SIZE
`define DCACHE_CRSQ_SIZE 4
`define DCACHE_CRSQ_SIZE 2
`endif
// Miss Handling Register Size
@ -552,7 +552,7 @@
// Core Response Queue Size
`ifndef TCACHE_CRSQ_SIZE
`define TCACHE_CRSQ_SIZE 4
`define TCACHE_CRSQ_SIZE 2
`endif
// Miss Handling Register Size
@ -616,7 +616,7 @@
// Core Response Queue Size
`ifndef RCACHE_CRSQ_SIZE
`define RCACHE_CRSQ_SIZE 4
`define RCACHE_CRSQ_SIZE 2
`endif
// Miss Handling Register Size
@ -680,7 +680,7 @@
// Core Response Queue Size
`ifndef OCACHE_CRSQ_SIZE
`define OCACHE_CRSQ_SIZE 4
`define OCACHE_CRSQ_SIZE 2
`endif
// Miss Handling Register Size
@ -731,7 +731,7 @@
// Core Response Queue Size
`ifndef L2_CRSQ_SIZE
`define L2_CRSQ_SIZE 4
`define L2_CRSQ_SIZE 2
`endif
// Miss Handling Register Size
@ -782,7 +782,7 @@
// Core Response Queue Size
`ifndef L3_CRSQ_SIZE
`define L3_CRSQ_SIZE 4
`define L3_CRSQ_SIZE 2
`endif
// Miss Handling Register Size

3
hw/rtl/VX_csr_unit.sv
View file

@ -245,8 +245,7 @@ module VX_csr_unit #(
// send response
VX_skid_buffer #(
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + `NUM_THREADS * 32),
.OUT_REG (1)
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + `NUM_THREADS * 32)
) rsp_sbuf (
.clk (clk),
.reset (reset),

2
hw/rtl/VX_gpu_unit.sv
View file

@ -296,7 +296,7 @@ module VX_gpu_unit #(
.NUM_INPUTS (RSP_ARB_SIZE),
.DATAW (RSP_ARB_DATAW),
.ARBITER ("R"),
.BUFFERED (2)
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (reset),

3
hw/rtl/VX_lsu_unit.sv
View file

@ -339,8 +339,7 @@ module VX_lsu_unit #(
// send load commit
VX_skid_buffer #(
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1),
.OUT_REG (1)
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1)
) rsp_sbuf (
.clk (clk),
.reset (reset),

40
hw/rtl/VX_mem_unit.sv
View file

@ -88,7 +88,9 @@ module VX_mem_unit # (
.MREQ_SIZE (`ICACHE_MREQ_SIZE),
.TAG_WIDTH (ICACHE_ARB_TAG_WIDTH),
.UUID_WIDTH (`UUID_BITS),
.WRITE_ENABLE (0)
.WRITE_ENABLE (0),
.CORE_OUT_REG (3),
.MEM_OUT_REG (3)
) icache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_icache_if),
@ -117,13 +119,13 @@ module VX_mem_unit # (
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
) dcache_smem_req_if [`NUM_SOCKETS]();
) dcache_nosm_req_if [`NUM_SOCKETS]();
VX_cache_rsp_if #(
.NUM_REQS (DCACHE_NUM_REQS),
.WORD_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
) dcache_smem_rsp_if [`NUM_SOCKETS]();
) dcache_nosm_rsp_if [`NUM_SOCKETS]();
`RESET_RELAY (dcache_reset, reset);
@ -148,7 +150,9 @@ module VX_mem_unit # (
.UUID_WIDTH (`UUID_BITS),
.WRITE_ENABLE (1),
.NC_ENABLE (1),
.NC_TAG_BIT (0)
.NC_TAG_BIT (0),
.CORE_OUT_REG (`SM_ENABLED ? 2 : 3),
.MEM_OUT_REG (3)
) dcache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_dcache_if),
@ -156,8 +160,8 @@ module VX_mem_unit # (
.clk (clk),
.reset (dcache_reset),
.core_req_if (dcache_smem_req_if),
.core_rsp_if (dcache_smem_rsp_if),
.core_req_if (dcache_nosm_req_if),
.core_rsp_if (dcache_nosm_rsp_if),
.mem_req_if (dcache_mem_req_if),
.mem_rsp_if (dcache_mem_rsp_if)
);
@ -190,7 +194,7 @@ module VX_mem_unit # (
.ARBITER ("P"),
.BUFFERED_REQ (2),
.BUFFERED_RSP (2)
) dcache_smem_switch (
) smem_switch (
.clk (clk),
.reset (dcache_smem_switch_reset),
.req_in_if (dcache_req_if[i]),
@ -199,8 +203,8 @@ module VX_mem_unit # (
.rsp_out_if (dcache_smem_switch_rsp_if)
);
`ASSIGN_VX_CACHE_REQ_IF (dcache_smem_req_if[i], dcache_smem_switch_req_if[0]);
`ASSIGN_VX_CACHE_RSP_IF (dcache_smem_switch_rsp_if[0], dcache_smem_rsp_if[i]);
`ASSIGN_VX_CACHE_REQ_IF (dcache_nosm_req_if[i], dcache_smem_switch_req_if[0]);
`ASSIGN_VX_CACHE_RSP_IF (dcache_smem_switch_rsp_if[0], dcache_nosm_rsp_if[i]);
// shared memory address mapping:
// [core_idx][warp_idx][word_idx][thread_idx] <= [core_idx][warp_idx][thread_idx][bank_offset..word_idx]
@ -237,7 +241,7 @@ module VX_mem_unit # (
.UUID_WIDTH (`UUID_BITS),
.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH),
.OUT_REG (2)
) smem (
) shared_mem (
.clk (clk),
.reset (smem_reset),
@ -265,8 +269,8 @@ module VX_mem_unit # (
`else
for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
`ASSIGN_VX_CACHE_REQ_IF (dcache_smem_req_if[i], dcache_req_if[i]);
`ASSIGN_VX_CACHE_RSP_IF (dcache_rsp_if[i], dcache_smem_rsp_if[i]);
`ASSIGN_VX_CACHE_REQ_IF (dcache_nosm_req_if[i], dcache_req_if[i]);
`ASSIGN_VX_CACHE_RSP_IF (dcache_rsp_if[i], dcache_nosm_rsp_if[i]);
end
`endif
@ -307,7 +311,9 @@ module VX_mem_unit # (
.TAG_WIDTH (TCACHE_TAG_WIDTH),
.WRITE_ENABLE (0),
.UUID_WIDTH (`UUID_BITS),
.NC_ENABLE (0)
.NC_ENABLE (0),
.CORE_OUT_REG (3),
.MEM_OUT_REG (3)
) tcache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_tcache_if),
@ -358,7 +364,9 @@ module VX_mem_unit # (
.TAG_WIDTH (OCACHE_TAG_WIDTH),
.WRITE_ENABLE (1),
.UUID_WIDTH (`UUID_BITS),
.NC_ENABLE (0)
.NC_ENABLE (0),
.CORE_OUT_REG (3),
.MEM_OUT_REG (3)
) ocache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_ocache_if),
@ -410,7 +418,9 @@ module VX_mem_unit # (
.TAG_WIDTH (RCACHE_TAG_WIDTH),
.WRITE_ENABLE (0),
.UUID_WIDTH (0),
.NC_ENABLE (0)
.NC_ENABLE (0),
.CORE_OUT_REG (3),
.MEM_OUT_REG (3)
) rcache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_rcache_if),

94
hw/rtl/cache/VX_bank.sv vendored
View file

@ -128,7 +128,7 @@ module VX_bank #(
.ready_out (creq_ready)
);
wire crsq_alm_full;
wire crsq_stall;
wire mreq_alm_full;
wire [`LINE_ADDR_WIDTH-1:0] mem_rsp_addr;
@ -162,9 +162,10 @@ module VX_bank #(
wire is_flush_st0;
wire mshr_pending_st0, mshr_pending_st1;
// prevent read-during-write hazard when accessing tags/data block RAMs
wire rdw_fill_hazard_st0 = valid_st0 && is_fill_st0;
reg pipe_enable;
wire rdw_hazard_st0;
reg rdw_hazard_st1;
wire pipe_stall = crsq_stall || rdw_hazard_st1;
// determine which input to select in priority order
wire mshr_grant = ~flush_enable;
@ -177,17 +178,16 @@ module VX_bank #(
wire creq_enable = creq_grant && creq_valid;
assign mshr_deq_ready = mshr_grant
&& ~rdw_fill_hazard_st0 // prevent read-during-write hazard
&& ~crsq_alm_full; // ensure core_rsp_queue not full
&& ~rdw_hazard_st0
&& ~pipe_stall;
assign mem_rsp_ready = mrsq_grant
&& pipe_enable;
&& ~pipe_stall;
assign creq_ready = creq_grant
&& ~mreq_alm_full // ensure mem_req_queue not full
&& ~crsq_alm_full // ensure core_rsp_queue not full
&& ~mshr_alm_full // ensure mshr not full
&& pipe_enable;
&& ~mreq_alm_full
&& ~mshr_alm_full
&& ~pipe_stall;
wire flush_fire = flush_enable;
wire mshr_deq_fire = mshr_deq_valid && mshr_deq_ready;
@ -210,7 +210,7 @@ module VX_bank #(
) pipe_reg0 (
.clk (clk),
.reset (reset),
.enable (pipe_enable),
.enable (~pipe_stall),
.data_in ({
flush_fire || mshr_deq_fire || mem_rsp_fire || creq_fire,
flush_enable,
@ -232,6 +232,8 @@ module VX_bank #(
`ASSIGN_REQ_UUID (req_uuid_st0, tag_st0[0])
wire do_read_st0 = valid_st0 && is_read_st0;
wire do_mshr_st0 = valid_st0 && is_mshr_st0;
wire do_fill_st0 = valid_st0 && is_fill_st0;
wire do_flush_st0 = valid_st0 && is_flush_st0;
wire do_lookup_st0 = valid_st0 && ~(is_fill_st0 || is_flush_st0);
@ -257,7 +259,7 @@ module VX_bank #(
.req_uuid (req_uuid_st0),
.stall (~pipe_enable),
.stall (pipe_stall),
// read/Fill
.lookup (do_lookup_st0),
@ -272,7 +274,7 @@ module VX_bank #(
assign is_hit_st0 = tag_match_st0;
// ensure mshr reply never get a miss
`RUNTIME_ASSERT (is_hit_st0 || ~(valid_st0 && is_mshr_st0), ("runtime error"));
`RUNTIME_ASSERT (is_hit_st0 || ~do_mshr_st0, ("runtime error"));
wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = is_read_st0 ? mshr_alloc_id : mshr_id_st0;
@ -282,17 +284,16 @@ module VX_bank #(
) pipe_reg1 (
.clk (clk),
.reset (reset),
.enable (pipe_enable),
.enable (~pipe_stall),
.data_in ({valid_st0, is_mshr_st0, is_fill_st0, is_read_st0, is_write_st0, is_hit_st0, way_sel_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_idx_st0, pmask_st0, tag_st0, mshr_id_a_st0, mshr_pending_st0}),
.data_out ({valid_st1, is_mshr_st1, is_fill_st1, is_read_st1, is_write_st1, is_hit_st1, way_sel_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_idx_st1, pmask_st1, tag_st1, mshr_id_st1, mshr_pending_st1})
);
`ASSIGN_REQ_UUID (req_uuid_st1, tag_st1[0])
wire do_read_st0 = valid_st0 && is_read_st0;
wire do_read_st1 = valid_st1 && is_read_st1;
wire do_write_st1 = valid_st1 && is_write_st1;
wire do_fill_st1 = valid_st1 && is_fill_st1;
wire do_fill_st1 = valid_st1 && is_fill_st1;
wire do_mshr_st1 = valid_st1 && is_mshr_st1;
wire do_read_hit_st1 = do_read_st1 && is_hit_st1;
@ -304,12 +305,10 @@ module VX_bank #(
`UNUSED_VAR (do_write_miss_st1)
// detect read during write data hazard
assign rdw_hazard_st0 = do_fill_st0;
always @(posedge clk) begin
if (reset) begin
pipe_enable <= 0;
end else begin
pipe_enable <= ~(do_read_st0 && do_write_hit_st1 && (addr_st0 == addr_st1) && pipe_enable);
end
rdw_hazard_st1 <= (do_read_st0 && do_write_hit_st1 && (addr_st0 == addr_st1))
&& ~rdw_hazard_st1;
end
wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data_st1 = wdata_st1[0 +: NUM_PORTS * `WORD_WIDTH];
@ -332,7 +331,7 @@ module VX_bank #(
.req_uuid (req_uuid_st1),
.stall (~pipe_enable),
.stall (pipe_stall),
.read (do_read_hit_st1 || do_mshr_st1),
.fill (do_fill_st1),
@ -348,10 +347,10 @@ module VX_bank #(
);
wire [MSHR_SIZE-1:0] mshr_matches;
wire mshr_allocate = do_read_st0;
wire mshr_replay = do_fill_st0;
wire mshr_allocate = do_read_st0 && ~pipe_stall;
wire mshr_replay = do_fill_st0 && ~pipe_stall;
wire mshr_lookup = mshr_allocate;
wire mshr_release = do_read_hit_st1 && pipe_enable;
wire mshr_release = do_read_hit_st1 && ~pipe_stall;
VX_pending_size #(
.SIZE (MSHR_SIZE)
@ -425,42 +424,34 @@ module VX_bank #(
// schedule core response
wire crsq_push, crsq_pop, crsq_empty;
wire crsq_valid, crsq_ready;
wire [NUM_PORTS-1:0] crsq_pmask;
wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] crsq_data;
wire [NUM_PORTS-1:0][REQ_SEL_WIDTH-1:0] crsq_idx;
wire [NUM_PORTS-1:0][TAG_WIDTH-1:0] crsq_tag;
assign crsq_push = (do_read_hit_st1 && pipe_enable)
|| do_mshr_st1;
assign crsq_pop = core_rsp_valid && core_rsp_ready;
assign crsq_valid = do_read_hit_st1 || do_mshr_st1;
assign crsq_pmask = pmask_st1;
assign crsq_idx = req_idx_st1;
assign crsq_data = rdata_st1;
assign crsq_tag = tag_st1;
VX_fifo_queue #(
.DATAW (NUM_PORTS * (TAG_WIDTH + 1 + `WORD_WIDTH + REQ_SEL_WIDTH)),
.SIZE (CRSQ_SIZE),
.ALM_FULL (CRSQ_SIZE-2),
.OUT_REG (CORE_OUT_REG)
VX_elastic_buffer #(
.DATAW (NUM_PORTS * (TAG_WIDTH + 1 + `WORD_WIDTH + REQ_SEL_WIDTH)),
.SIZE (CRSQ_SIZE),
.OUT_REG (CORE_OUT_REG)
) core_rsp_queue (
.clk (clk),
.reset (reset),
.push (crsq_push),
.pop (crsq_pop),
.data_in ({crsq_tag, crsq_pmask, crsq_data, crsq_idx}),
.data_out ({core_rsp_tag, core_rsp_pmask, core_rsp_data, core_rsp_idx}),
.empty (crsq_empty),
.alm_full (crsq_alm_full),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
.clk (clk),
.reset (reset),
.valid_in (crsq_valid && ~rdw_hazard_st1),
.ready_in (crsq_ready),
.data_in ({crsq_tag, crsq_pmask, crsq_data, crsq_idx}),
.data_out ({core_rsp_tag, core_rsp_pmask, core_rsp_data, core_rsp_idx}),
.valid_out (core_rsp_valid),
.ready_out (core_rsp_ready)
);
assign core_rsp_valid = ~crsq_empty;
assign crsq_stall = crsq_valid && ~crsq_ready;
// schedule memory request
@ -516,12 +507,13 @@ module VX_bank #(
`endif
`ifdef DBG_TRACE_CACHE_BANK
wire crsq_fire = crsq_valid && crsq_ready;
wire pipeline_stall = (mshr_deq_valid || mem_rsp_valid || creq_valid)
&& ~(mshr_deq_fire || mem_rsp_fire || creq_fire);
always @(posedge clk) begin
if (pipeline_stall) begin
`TRACE(3, ("%d: *** %s:%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsq_alm_full, mreq_alm_full, mshr_alm_full));
`TRACE(3, ("%d: *** %s:%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full));
end
if (flush_enable) begin
`TRACE(2, ("%d: %s:%0d flush: addr=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(flush_addr, BANK_ID)));
@ -538,7 +530,7 @@ module VX_bank #(
else
`TRACE(2, ("%d: %s:%0d core-rd-req: addr=0x%0h, tag=0x%0h, pmask=%b, tid=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_idx, req_uuid_sel));
end
if (crsq_push) begin
if (crsq_fire) begin
`TRACE(2, ("%d: %s:%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, pmask=%b, tid=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_pmask, crsq_idx, crsq_data, req_uuid_st1));
end
if (mreq_push) begin

26
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -45,7 +45,13 @@ module VX_cache_cluster #(
// enable bypass for non-cacheable addresses
parameter NC_TAG_BIT = 0,
parameter NC_ENABLE = 0
parameter NC_ENABLE = 0,
// Core response output register
parameter CORE_OUT_REG = 0,
// Memory request output register
parameter MEM_OUT_REG = 0
) (
input wire clk,
input wire reset,
@ -115,7 +121,7 @@ module VX_cache_cluster #(
.TAG_SEL_IDX (TAG_SEL_IDX),
.ARBITER ("R"),
.BUFFERED_REQ ((NUM_INPUTS != NUM_CACHES) ? 2 : 0),
.BUFFERED_RSP ((NUM_INPUTS != NUM_CACHES) ? 2 : 0)
.BUFFERED_RSP ((NUM_INPUTS != NUM_CACHES) ? ((CORE_OUT_REG + 1) / 2) : 0)
) cache_arb (
.clk (clk),
.reset (cache_arb_reset),
@ -164,8 +170,8 @@ module VX_cache_cluster #(
.WRITE_ENABLE (WRITE_ENABLE),
.UUID_WIDTH (UUID_WIDTH),
.TAG_WIDTH (ARB_TAG_WIDTH),
.CORE_OUT_REG (3),
.MEM_OUT_REG (2),
.CORE_OUT_REG ((NUM_INPUTS != NUM_CACHES) ? 2 : CORE_OUT_REG),
.MEM_OUT_REG ((NUM_CACHES > 1) ? 2 : MEM_OUT_REG),
.NC_ENABLE (NC_ENABLE),
.PASSTHRU (PASSTHRU)
) cache_wrap (
@ -191,7 +197,7 @@ module VX_cache_cluster #(
.TAG_WIDTH (MEM_TAG_WIDTH),
.TAG_SEL_IDX (1), // Skip 0 for NC flag
.ARBITER ("R"),
.BUFFERED_REQ ((NUM_CACHES > 1) ? 2 : 0),
.BUFFERED_REQ ((NUM_CACHES > 1) ? ((MEM_OUT_REG + 1) / 2) : 0),
.BUFFERED_RSP ((NUM_CACHES > 1) ? 2 : 0)
) mem_arb (
.clk (clk),
@ -253,6 +259,12 @@ module VX_cache_cluster_top #(
parameter NC_TAG_BIT = 0,
parameter NC_ENABLE = 1,
// Core response output register
parameter CORE_OUT_REG = 3,
// Memory request output register
parameter MEM_OUT_REG = 3,
parameter NUM_CACHES = `UP(NUM_UNITS),
parameter PASSTHRU = (NUM_UNITS == 0),
parameter ARB_TAG_WIDTH = TAG_WIDTH + `ARB_SEL_BITS(NUM_INPUTS, NUM_CACHES),
@ -370,7 +382,9 @@ module VX_cache_cluster_top #(
.UUID_WIDTH (UUID_WIDTH),
.WRITE_ENABLE (WRITE_ENABLE),
.NC_TAG_BIT (NC_TAG_BIT),
.NC_ENABLE (NC_ENABLE)
.NC_ENABLE (NC_ENABLE),
.CORE_OUT_REG (CORE_OUT_REG),
.MEM_OUT_REG (MEM_OUT_REG)
) cache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_icache_if),

14
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -39,18 +39,18 @@ module VX_cache_wrap #(
// core request tag size
parameter TAG_WIDTH = UUID_WIDTH + 1,
// Core response output register
parameter CORE_OUT_REG = 0,
// Memory request output register
parameter MEM_OUT_REG = 0,
// enable bypass for non-cacheable addresses
parameter NC_TAG_BIT = 0,
parameter NC_ENABLE = 0,
// Force bypass for all requests
parameter PASSTHRU = 0
parameter PASSTHRU = 0,
// Core response output register
parameter CORE_OUT_REG = 0,
// Memory request output register
parameter MEM_OUT_REG = 0
) (
input wire clk,

3
hw/rtl/fpu_unit/VX_fpu_agent.sv
View file

@ -107,8 +107,7 @@ module VX_fpu_agent #(
// commit
VX_skid_buffer #(
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + (`NUM_THREADS * 32)),
.OUT_REG (1)
.DATAW (UUID_WIDTH + NW_WIDTH + `NUM_THREADS + 32 + `NR_BITS + (`NUM_THREADS * 32))
) rsp_sbuf (
.clk (clk),
.reset (reset),

8
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -51,7 +51,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
end else if (NUM_REQS == 3) begin
end /*else if (NUM_REQS == 3) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
@ -81,7 +81,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
end else if (NUM_REQS == 4) begin
end */else if (NUM_REQS == 4) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
@ -117,7 +117,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
end else if (NUM_REQS == 5) begin
end /*else if (NUM_REQS == 5) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
@ -281,7 +281,7 @@ module VX_rr_arbiter #(
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
end else if (NUM_REQS == 8) begin
end */else if (NUM_REQS == 8) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;

4
hw/syn/altera/opae/vortex_afu.json
View file

@ -2,8 +2,8 @@
"version": 1,
"afu-image": {
"power": 0,
"clock-frequency-high": "auto",
"clock-frequency-low": "auto",
"clock-frequency-high": "auto-250",
"clock-frequency-low": "auto-125",
"cmd-mem-read": 1,
"cmd-mem-write": 2,

1
hw/syn/altera/quartus/top-gfx/Makefile
View file

@ -8,6 +8,7 @@ CONFIGS += -set "NOPAE"
CONFIGS += -set "EXT_GFX_ENABLE"
CONFIGS += -set "NUM_CORES=16"
CONFIGS += -set "NUM_CLUSTERS=1"
CONFIGS += -set "L2_ENABLE"