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minor update

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This commit is contained in:
Blaise Tine 2024-10-13 16:22:59 -07:00
parent 9e5638c9b0
commit f63233334e
3 changed files with 37 additions and 25 deletions
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2
hw/rtl/cache/VX_cache_mshr.sv vendored
View file

@ -215,7 +215,7 @@ module VX_cache_mshr #(
`RUNTIME_ASSERT(~(finalize_valid && ~valid_table[finalize_id]), ("%t: *** %s invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID,
`CS_LINE_TO_FULL_ADDR(addr_table[finalize_id], BANK_ID), finalize_id, fin_req_uuid))
`RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID,
`RUNTIME_ASSERT(~(fill_valid && ~valid_table[fill_id]), ("%t: *** %s invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID,
`CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), fill_id))
VX_dp_ram #(

22
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -135,7 +135,7 @@ module VX_axi_adapter #(
);
end
wire tbuf_full;
wire mem_req_tag_ready;
wire [TAG_WIDTH_OUT-1:0] mem_req_tag_out;
wire [TAG_WIDTH_OUT-1:0] mem_rsp_tag_out;
@ -143,13 +143,14 @@ module VX_axi_adapter #(
if (TAG_WIDTH_IN > TAG_WIDTH_OUT) begin : g_tag_buf
localparam TBUF_ADDRW = `CLOG2(TAG_BUFFER_SIZE);
wire [TBUF_ADDRW-1:0] tbuf_waddr, tbuf_raddr;
wire tbuf_full;
VX_index_buffer #(
.DATAW (TAG_WIDTH_IN),
.SIZE (TAG_BUFFER_SIZE)
) tag_buf (
.clk (clk),
.reset (reset),
.acquire_en (mem_req_valid && !mem_req_rw && mem_req_ready),
.acquire_en (mem_req_valid && ~mem_req_rw && mem_req_ready),
.write_addr (tbuf_waddr),
.write_data (mem_req_tag),
.read_data (mem_rsp_tag),
@ -158,22 +159,24 @@ module VX_axi_adapter #(
.full (tbuf_full),
`UNUSED_PIN (empty)
);
assign mem_req_tag_ready = mem_req_rw || ~tbuf_full;
assign mem_req_tag_out = TAG_WIDTH_OUT'(tbuf_waddr);
assign tbuf_raddr = mem_rsp_tag_out[TBUF_ADDRW-1:0];
`UNUSED_VAR (mem_rsp_tag_out)
end else begin : g_no_tag_buf
assign tbuf_full = 0;
assign mem_req_tag_ready = 1;
assign mem_req_tag_out = TAG_WIDTH_OUT'(mem_req_tag);
assign mem_rsp_tag = mem_rsp_tag_out[TAG_WIDTH_IN-1:0];
`UNUSED_VAR (mem_rsp_tag_out)
end
// request ack
assign mem_req_ready = (mem_req_rw ? axi_write_ready[req_bank_sel] : m_axi_arready[req_bank_sel]) && ~tbuf_full;
assign mem_req_ready = mem_req_rw ? axi_write_ready[req_bank_sel] :
(m_axi_arready[req_bank_sel] && mem_req_tag_ready);
// AXI write request address channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_addr
assign m_axi_awvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~tbuf_full && ~m_axi_aw_ack[i];
assign m_axi_awvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_aw_ack[i];
assign m_axi_awaddr[i] = ADDR_WIDTH_OUT'(req_bank_off) << `CLOG2(DATA_WIDTH/8);
assign m_axi_awid[i] = mem_req_tag_out;
assign m_axi_awlen[i] = 8'b00000000;
@ -188,7 +191,7 @@ module VX_axi_adapter #(
// AXI write request data channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_write_data
assign m_axi_wvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~tbuf_full && ~m_axi_w_ack[i];
assign m_axi_wvalid[i] = mem_req_valid && mem_req_rw && (req_bank_sel == i) && ~m_axi_w_ack[i];
assign m_axi_wdata[i] = mem_req_data;
assign m_axi_wstrb[i] = mem_req_byteen;
assign m_axi_wlast[i] = 1'b1;
@ -205,7 +208,7 @@ module VX_axi_adapter #(
// AXI read request channel
for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_axi_read_req
assign m_axi_arvalid[i] = mem_req_valid && ~mem_req_rw && (req_bank_sel == i) && ~tbuf_full;
assign m_axi_arvalid[i] = mem_req_valid && ~mem_req_rw && (req_bank_sel == i) && mem_req_tag_ready;
assign m_axi_araddr[i] = ADDR_WIDTH_OUT'(req_bank_off) << `CLOG2(DATA_WIDTH/8);
assign m_axi_arid[i] = mem_req_tag_out;
assign m_axi_arlen[i] = 8'b00000000;
@ -228,9 +231,8 @@ module VX_axi_adapter #(
assign rsp_arb_valid_in[i] = m_axi_rvalid[i];
assign rsp_arb_data_in[i] = {m_axi_rdata[i], m_axi_rid[i]};
assign m_axi_rready[i] = rsp_arb_ready_in[i];
`RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rlast[i] == 1, ("%t: *** AXI response error", $time))
`RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rresp[i] == 0, ("%t: *** AXI response error", $time))
`UNUSED_VAR (m_axi_rlast[i])
`RUNTIME_ASSERT(~(m_axi_rvalid[i] && m_axi_rlast[i] == 0), ("%t: *** AXI response error", $time))
`RUNTIME_ASSERT(~(m_axi_rvalid[i] && m_axi_rresp[i] != 0), ("%t: *** AXI response error", $time))
end
VX_stream_arb #(

38
sim/xrtsim/xrt_sim.cpp
View file

@ -333,6 +333,8 @@ private:
}
device_->ap_rst_n = 1;
// this AXI device is always ready to accept new requests
for (int i = 0; i < PLATFORM_MEMORY_BANKS; ++i) {
*m_axi_mem_[i].arready = 1;
*m_axi_mem_[i].awready = 1;
@ -381,53 +383,56 @@ private:
}
void axi_ctrl_bus_reset() {
// address read request
// read request address
device_->s_axi_ctrl_arvalid = 0;
device_->s_axi_ctrl_araddr = 0;
// data read response
// read response
device_->s_axi_ctrl_rready = 0;
// address write request
// write request address
device_->s_axi_ctrl_awvalid = 0;
device_->s_axi_ctrl_awaddr = 0;
// data write request
// write request data
device_->s_axi_ctrl_wvalid = 0;
device_->s_axi_ctrl_wdata = 0;
device_->s_axi_ctrl_wstrb = 0;
// data write response
// write response
device_->s_axi_ctrl_bready = 0;
}
void axi_mem_bus_reset() {
for (int i = 0; i < PLATFORM_MEMORY_BANKS; ++i) {
// address read request
// read request address
*m_axi_mem_[i].arready = 0;
// address write request
// write request address
*m_axi_mem_[i].awready = 0;
// data write request
// write request data
*m_axi_mem_[i].wready = 0;
// data read response
// read response
*m_axi_mem_[i].rvalid = 0;
// data write response
// write response
*m_axi_mem_[i].bvalid = 0;
// states
m_axi_states_[i].write_req_pending = false;
m_axi_states_[i].write_rsp_pending = false;
m_axi_states_[i].read_rsp_pending = false;
}
}
void axi_mem_bus_eval() {
for (int i = 0; i < PLATFORM_MEMORY_BANKS; ++i) {
// handle read responses
if (*m_axi_mem_[i].rvalid && *m_axi_mem_[i].rready) {
*m_axi_mem_[i].rvalid = 0;
if (*m_axi_mem_[i].rvalid && (*m_axi_mem_[i].rready || ~m_axi_states_[i].read_rsp_pending)) {
*m_axi_mem_[i].rvalid = 0;
m_axi_states_[i].read_rsp_pending = false;
}
if (!*m_axi_mem_[i].rvalid) {
if (!pending_mem_reqs_[i].empty()
@ -441,13 +446,15 @@ private:
*m_axi_mem_[i].rlast = 1;
memcpy(m_axi_mem_[i].rdata->data(), mem_rsp->data.data(), PLATFORM_MEMORY_DATA_SIZE);
pending_mem_reqs_[i].erase(mem_rsp_it);
m_axi_states_[i].read_rsp_pending = !*m_axi_mem_[i].rready;
delete mem_rsp;
}
}
// handle write responses
if (*m_axi_mem_[i].bvalid && *m_axi_mem_[i].bready) {
if (*m_axi_mem_[i].bvalid && (*m_axi_mem_[i].bready || ~m_axi_states_[i].write_rsp_pending)) {
*m_axi_mem_[i].bvalid = 0;
m_axi_states_[i].write_rsp_pending = false;
}
if (!*m_axi_mem_[i].bvalid) {
if (!pending_mem_reqs_[i].empty()
@ -459,6 +466,7 @@ private:
*m_axi_mem_[i].bid = mem_rsp->tag;
*m_axi_mem_[i].bresp = 0;
pending_mem_reqs_[i].erase(mem_rsp_it);
m_axi_states_[i].write_rsp_pending = !*m_axi_mem_[i].bready;
delete mem_rsp;
}
}
@ -487,7 +495,7 @@ private:
*m_axi_mem_[i].wready = 0;
}
// handle address write requestsls
// handle address write requestsls
if (*m_axi_mem_[i].awvalid && *m_axi_mem_[i].awready && !*m_axi_mem_[i].wready) {
m_axi_states_[i].write_req_addr = *m_axi_mem_[i].awaddr;
m_axi_states_[i].write_req_tag = *m_axi_mem_[i].awid;
@ -537,6 +545,8 @@ private:
uint64_t write_req_addr;
uint32_t write_req_tag;
bool write_req_pending;
bool write_rsp_pending;
bool read_rsp_pending;
} m_axi_state_t;
typedef struct {