mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
simX within 30% cycles of the RTL for matAdd
This commit is contained in:
felsabbagh3
parent
92e88a7bb2
commit
f717ff56da
9 changed files with 605 additions and 73 deletions
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@ -13,8 +13,9 @@ LIB=
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CF=-CFLAGS '-std=c++11 -fPIC -O3'
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LIGHTW=-Wno-UNOPTFLAT -Wno-BLKLOOPINIT
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DEB=--trace --prof-cfuncs -DVL_DEBUG=1
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EXE=--exe $(LIB_OBJS)
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all: simX
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# simX:
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@ -22,7 +23,7 @@ all: simX
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simX:
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verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW)
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verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) $(DEB)
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(cd obj_dir && make -j -f Vcache_simX.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
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clean:
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@ -93,25 +93,26 @@ module cache_simX (
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always @(posedge clk, posedge reset) begin
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if (reset)
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begin
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icache_i_m_ready <= 0;
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dcache_i_m_ready <= 0;
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icache_i_m_ready = 0;
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dcache_i_m_ready = 0;
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end else begin
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if (VX_dram_req_rsp_icache.o_m_valid) begin
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icache_i_m_ready <= 1;
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icache_i_m_ready = 1;
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// $display("cache_simX.v: setting icache_i_m_ready = %d", icache_i_m_ready);
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end else if (icache_i_m_ready) begin
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icache_i_m_ready <= 0;
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icache_i_m_ready = 0;
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end else begin
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icache_i_m_ready <= 0;
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icache_i_m_ready = 0;
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end
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if (VX_dram_req_rsp.o_m_valid) begin
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dcache_i_m_ready <= 1;
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dcache_i_m_ready = 1;
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end else if (dcache_i_m_ready) begin
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dcache_i_m_ready <= 0;
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dcache_i_m_ready = 0;
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end else begin
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dcache_i_m_ready <= 0;
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dcache_i_m_ready = 0;
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end
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end
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584
simX/core.cpp
584
simX/core.cpp
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@ -20,9 +20,74 @@
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#include "include/qsim-harp.h"
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#endif
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#define NO_MEM_READ 7
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#define LB_MEM_READ 0
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#define LH_MEM_READ 1
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#define LW_MEM_READ 2
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#define LBU_MEM_READ 4
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#define LHU_MEM_READ 5
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#define NO_MEM_WRITE 7
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#define SB_MEM_WRITE 0
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#define SH_MEM_WRITE 1
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#define SW_MEM_WRITE 2
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#define INIT_TRACE(trace_inst) \
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trace_inst.valid_inst = false; \
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trace_inst.pc = 0; \
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trace_inst.wid = schedule_w; \
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trace_inst.rs1 = -1; \
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trace_inst.rs2 = -1; \
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trace_inst.rd = -1; \
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trace_inst.is_lw = false; \
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trace_inst.is_sw = false; \
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trace_inst.mem_addresses = new unsigned[a.getNThds()]; \
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for (int tid = 0; tid < a.getNThds(); tid++) trace_inst.mem_addresses[tid] = 0xdeadbeef; \
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trace_inst.mem_stall_cycles = 0; \
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trace_inst.fetch_stall_cycles = 0; \
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trace_inst.stall_warp = false; \
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trace_inst.wspawn = false; \
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trace_inst.stalled = false;
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#define CPY_TRACE(drain, source) \
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drain.valid_inst = source.valid_inst; \
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drain.pc = source.pc; \
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drain.wid = source.wid; \
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drain.rs1 = source.rs1; \
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drain.rs2 = source.rs2; \
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drain.rd = source.rd; \
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drain.is_lw = source.is_lw; \
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drain.is_sw = source.is_sw; \
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for (int tid = 0; tid < a.getNThds(); tid++) drain.mem_addresses[tid] = source.mem_addresses[tid]; \
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drain.mem_stall_cycles = source.mem_stall_cycles; \
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drain.fetch_stall_cycles = source.fetch_stall_cycles; \
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drain.stall_warp = source.stall_warp; \
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drain.wspawn = source.wspawn; \
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drain.stalled = false;
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using namespace Harp;
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using namespace std;
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void printTrace(trace_inst_t * trace, const char * stage_name)
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{
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cout << "********************************** " << stage_name << " *********************************\n";
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cout << "valid: " << trace->valid_inst << '\n';
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cout << "PC: " << hex << trace->pc << dec << '\n';
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cout << "wid: " << trace->wid << '\n';
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cout << "rd: " << trace->rd << "\trs1: " << trace->rs1 << "\trs2: " << trace->rs2 << '\n';
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cout << "is_lw: " << trace->is_lw << '\n';
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cout << "is_sw: " << trace->is_sw << '\n';
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cout << "fetch_stall_cycles: " << trace->fetch_stall_cycles << '\n';
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cout << "mem_stall_cycles: " << trace->mem_stall_cycles << '\n';
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cout << "stall_warp: " << trace->stall_warp << '\n';
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cout << "wspawn: " << trace->wspawn << '\n';
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cout << "stalled: " << trace->stalled << '\n';
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}
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#ifdef EMU_INSTRUMENTATION
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void Harp::reg_doRead(Word cpuId, Word regNum) {
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Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, true);
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@ -34,10 +99,45 @@ void Harp::reg_doWrite(Word cpuId, Word regNum) {
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#endif
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Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
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a(a), iDec(d), mem(mem), steps(0)
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a(a), iDec(d), mem(mem), steps(4)
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{
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release_warp = false;
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foundSchedule = true;
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schedule_w = 0;
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INIT_TRACE(inst_in_fetch);
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INIT_TRACE(inst_in_decode);
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INIT_TRACE(inst_in_scheduler);
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INIT_TRACE(inst_in_exe);
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INIT_TRACE(inst_in_lsu);
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INIT_TRACE(inst_in_wb);
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for (int i = 0; i < 32; i++)
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{
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stallWarp[i] = false;
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for (int j = 0; j < 32; j++)
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{
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renameTable[i][j] = true;
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}
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}
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cache_simulator = new Vcache_simX;
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m_trace = new VerilatedVcdC;
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cache_simulator->trace(m_trace, 99);
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m_trace->open("simXtrace.vcd");
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cache_simulator->reset = 1;
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cache_simulator->clk = 0;
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cache_simulator->eval();
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// m_trace->dump(10);
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cache_simulator->reset = 1;
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cache_simulator->clk = 1;
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cache_simulator->eval();
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// m_trace->dump(11);
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cache_simulator->reset = 0;
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cache_simulator->clk = 0;
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for (unsigned i = 0; i < a.getNWarps(); ++i)
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w.push_back(Warp(this, i));
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@ -51,54 +151,270 @@ bool Core::interrupt(Word r0) {
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void Core::step()
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{
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cout << "\n\n\n------------------------------------------------------\n";
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steps++;
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cout << "CYCLE: " << steps << '\n';
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cout << "Stalled Warps:\n";
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for (int widd = 0; widd < a.getNWarps(); widd++)
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{
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cout << stallWarp[widd] << " ";
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}
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cout << '\n';
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// cout << "Rename table\n";
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// for (int regii = 0; regii < 32; regii++)
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// {
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// cout << regii << ": " << renameTable[0][regii] << '\n';
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// }
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cout << '\n';
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this->writeback();
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this->load_store();
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this->execute_unit();
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this->scheduler();
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this->decode();
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this->fetch();
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if (release_warp)
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{
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release_warp = false;
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stallWarp[release_warp_num] = false;
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}
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}
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void Core::getCacheDelays(trace_inst_t * trace_inst)
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{
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static int curr_cycle = 0;
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if (trace_inst->valid_inst)
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{
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bool in_dcache_in_valid[a.getNThds()];
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unsigned in_dcache_in_address[a.getNThds()];
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unsigned in_dcache_mem_read;
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unsigned in_dcache_mem_write;
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if (trace_inst->is_lw)
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{
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in_dcache_mem_read = LW_MEM_READ;
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in_dcache_mem_write = NO_MEM_WRITE;
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}
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else if (trace_inst->is_sw)
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{
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in_dcache_mem_read = NO_MEM_READ;
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in_dcache_mem_write = SW_MEM_WRITE;
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}
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else
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{
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in_dcache_mem_read = NO_MEM_READ;
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in_dcache_mem_write = NO_MEM_WRITE;
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}
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for (int j = 0; j < a.getNThds(); j++)
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{
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if ((w[trace_inst->wid].tmask[j]) && (trace_inst->is_sw || trace_inst->is_lw))
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{
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in_dcache_in_valid[j] = true;
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in_dcache_in_address[j] = trace_inst->mem_addresses[j];
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}
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else
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{
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in_dcache_in_valid[j] = false;
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in_dcache_in_address[j] = 0xdeadbeef;
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}
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}
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cache_simulator->clk = 1;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle);
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cache_simulator->in_icache_pc_addr = trace_inst->pc;
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cache_simulator->in_icache_valid_pc_addr = 1;
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// DCache start
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cache_simulator->in_dcache_mem_read = in_dcache_mem_read;
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cache_simulator->in_dcache_mem_write = in_dcache_mem_write;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
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cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t];
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}
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// DCache end
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cache_simulator->clk = 0;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle+1);
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curr_cycle++;
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while((cache_simulator->out_icache_stall || cache_simulator->out_dcache_stall))
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{
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////////// Feed input
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if (cache_simulator->out_icache_stall)
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{
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cache_simulator->in_icache_pc_addr = trace_inst->pc;
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cache_simulator->in_icache_valid_pc_addr = 1;
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trace_inst->fetch_stall_cycles++;
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}
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else
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{
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cache_simulator->in_icache_valid_pc_addr = 0;
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}
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if (cache_simulator->out_dcache_stall)
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{
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cache_simulator->in_dcache_mem_read = in_dcache_mem_read;
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cache_simulator->in_dcache_mem_write = in_dcache_mem_write;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
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cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t];
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}
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trace_inst->mem_stall_cycles++;
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}
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else
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{
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cache_simulator->in_dcache_mem_read = NO_MEM_READ;
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cache_simulator->in_dcache_mem_write = NO_MEM_WRITE;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = 0;
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}
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}
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cache_simulator->clk = 1;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle);
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//////// Feed input
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if (cache_simulator->out_icache_stall)
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{
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cache_simulator->in_icache_pc_addr = trace_inst->pc;
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cache_simulator->in_icache_valid_pc_addr = 1;
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}
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else
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{
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cache_simulator->in_icache_valid_pc_addr = 0;
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}
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if (cache_simulator->out_dcache_stall)
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{
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cache_simulator->in_dcache_mem_read = in_dcache_mem_read;
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cache_simulator->in_dcache_mem_write = in_dcache_mem_write;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = in_dcache_in_valid[cur_t];
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cache_simulator->in_dcache_in_address[cur_t] = in_dcache_in_address[cur_t];
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}
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}
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else
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{
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cache_simulator->in_dcache_mem_read = NO_MEM_READ;
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cache_simulator->in_dcache_mem_write = NO_MEM_WRITE;
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for (int cur_t = 0; cur_t < a.getNThds(); cur_t++)
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{
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cache_simulator->in_dcache_in_valid[cur_t] = 0;
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}
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}
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cache_simulator->clk = 0;
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cache_simulator->eval();
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m_trace->dump(2*curr_cycle+1);
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curr_cycle++;
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}
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}
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}
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void Core::warpScheduler()
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{
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int numSteps = 0;
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bool cont;
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do
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{
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numSteps++;
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schedule_w = (schedule_w+1) % w.size();
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bool has_active_threads = (w[schedule_w].activeThreads > 0);
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bool stalled = stallWarp[schedule_w];
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cont = ((!has_active_threads) || (stalled)) && (numSteps <= w.size());
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// cout << "&&&&&&&WID: " << schedule_w << '\n';
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// cout << "activeThreads: " << w[schedule_w].activeThreads << "\t!has_active_threads: " << (!has_active_threads) << '\n';
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// cout << "stalled: " << stalled << '\n';
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// cout << "numSteps: " << numSteps << " CONT: " << cont << '\n';
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} while (cont);
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if (numSteps > w.size())
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{
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this->foundSchedule = false;
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}
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else
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{
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this->foundSchedule = true;
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}
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}
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void Core::fetch()
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{
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++steps;
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#ifdef PRINT_ACTIVE_THREADS
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cout << endl << "Threads:";
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#endif
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// D(-1, "Found schedule: " << foundSchedule);
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for (unsigned i = 0; i < w.size(); ++i) {
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if (w[i].activeThreads) {
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if ((!inst_in_scheduler.stalled) && (inst_in_fetch.fetch_stall_cycles == 0))
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{
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// CPY_TRACE(inst_in_decode, inst_in_fetch);
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// if (w[schedule_w].activeThreads)
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{
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trace_inst_t trace_inst;
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trace_inst.valid_inst = false;
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trace_inst.pc = 0;
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trace_inst.wid = i;
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trace_inst.rs1 = -1;
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trace_inst.rs2 = -1;
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trace_inst.rd = -1;
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trace_inst.is_lw = false;
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trace_inst.is_sw = false;
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trace_inst.mem_addresses = new unsigned[a.getNThds()];
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trace_inst.mem_stall_cycles = 0;
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trace_inst.fetch_stall_cycles = 0;
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trace_inst.stall_warp = false;
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D(3, "Core step stepping warp " << i << '[' << w[i].activeThreads << ']');
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w[i].step(&trace_inst);
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D(3, "Now " << w[i].activeThreads << " active threads in " << i);
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D(-1, "********************************");
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D(-1, "*** valid: " << trace_inst.valid_inst << " pc: " << hex << trace_inst.pc << dec << " rs1..rs2..rd " << trace_inst.rs1 << ".." << trace_inst.rs2 << ".." << trace_inst.rd << "\n");
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D(-1, "********************************");
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INIT_TRACE(inst_in_fetch);
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if (foundSchedule)
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{
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D(3, "Core step stepping warp " << schedule_w << '[' << w[schedule_w].activeThreads << ']');
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w[schedule_w].step(&inst_in_fetch);
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D(3, "Now " << w[schedule_w].activeThreads << " active threads in " << schedule_w);
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this->getCacheDelays(&inst_in_fetch);
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if (inst_in_fetch.stall_warp)
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{
|
||||
stallWarp[inst_in_fetch.wid] = true;
|
||||
}
|
||||
}
|
||||
warpScheduler();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
inst_in_fetch.stalled = false;
|
||||
if (inst_in_fetch.fetch_stall_cycles > 0) inst_in_fetch.fetch_stall_cycles--;
|
||||
}
|
||||
|
||||
printTrace(&inst_in_fetch, "Fetch");
|
||||
|
||||
#ifdef PRINT_ACTIVE_THREADS
|
||||
for (unsigned j = 0; j < w[i].tmask.size(); ++j) {
|
||||
if (w[i].activeThreads > j && w[i].tmask[j]) cout << " 1";
|
||||
else cout << " 0";
|
||||
if (j != w[i].tmask.size()-1 || i != w.size()-1) cout << ',';
|
||||
}
|
||||
#endif
|
||||
}
|
||||
// #ifdef PRINT_ACTIVE_THREADS
|
||||
// for (unsigned j = 0; j < w[schedule_w].tmask.size(); ++j) {
|
||||
// if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j]) cout << " 1";
|
||||
// else cout << " 0";
|
||||
// if (j != w[schedule_w].tmask.size()-1 || schedule_w != w.size()-1) cout << ',';
|
||||
// }
|
||||
// #endif
|
||||
|
||||
|
||||
|
||||
#ifdef PRINT_ACTIVE_THREADS
|
||||
cout << endl;
|
||||
#endif
|
||||
|
|
@ -107,31 +423,198 @@ void Core::fetch()
|
|||
void Core::decode()
|
||||
{
|
||||
|
||||
|
||||
|
||||
if ((inst_in_fetch.fetch_stall_cycles == 0) && !inst_in_scheduler.stalled)
|
||||
{
|
||||
CPY_TRACE(inst_in_decode, inst_in_fetch);
|
||||
INIT_TRACE(inst_in_fetch);
|
||||
}
|
||||
|
||||
printTrace(&inst_in_decode, "Decode");
|
||||
}
|
||||
|
||||
void Core::scheduler()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void Core::gpr_read()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void Core::execute_unit()
|
||||
{
|
||||
if (!inst_in_scheduler.stalled)
|
||||
{
|
||||
CPY_TRACE(inst_in_scheduler, inst_in_decode);
|
||||
INIT_TRACE(inst_in_decode);
|
||||
}
|
||||
|
||||
printTrace(&inst_in_scheduler, "scheduler");
|
||||
}
|
||||
|
||||
void Core::load_store()
|
||||
{
|
||||
bool do_nothing = false;
|
||||
if ((inst_in_lsu.mem_stall_cycles > 0) || (inst_in_lsu.stalled))
|
||||
{
|
||||
// LSU currently busy
|
||||
if ((inst_in_scheduler.is_lw || inst_in_scheduler.is_sw))
|
||||
{
|
||||
inst_in_scheduler.stalled = true;
|
||||
}
|
||||
do_nothing = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
// LSU not busy
|
||||
if (inst_in_scheduler.is_lw || inst_in_scheduler.is_sw)
|
||||
{
|
||||
// Scheduler has LSU inst
|
||||
bool scheduler_srcs_ready = true;
|
||||
if (inst_in_scheduler.rs1 > 0)
|
||||
{
|
||||
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs1];
|
||||
}
|
||||
|
||||
if (inst_in_scheduler.rs2 > 0)
|
||||
{
|
||||
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2];
|
||||
}
|
||||
|
||||
if (scheduler_srcs_ready)
|
||||
{
|
||||
if (inst_in_scheduler.rd != -1) renameTable[inst_in_scheduler.wid][inst_in_scheduler.rd] = false;
|
||||
CPY_TRACE(inst_in_lsu, inst_in_scheduler);
|
||||
INIT_TRACE(inst_in_scheduler);
|
||||
}
|
||||
else
|
||||
{
|
||||
inst_in_scheduler.stalled = true;
|
||||
// INIT_TRACE(inst_in_lsu);
|
||||
do_nothing = true;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// INIT_TRACE(inst_in_lsu);
|
||||
do_nothing = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (inst_in_lsu.mem_stall_cycles > 0) inst_in_lsu.mem_stall_cycles--;
|
||||
|
||||
printTrace(&inst_in_lsu, "LSU");
|
||||
}
|
||||
|
||||
void Core::execute_unit()
|
||||
{
|
||||
// cout << "$$$$$$$$$$$$$$$$$$$ EXE START\n";
|
||||
bool do_nothing = false;
|
||||
// EXEC is always not busy
|
||||
if (inst_in_scheduler.is_lw || inst_in_scheduler.is_sw)
|
||||
{
|
||||
// Not an execute instruction
|
||||
// INIT_TRACE(inst_in_exe);
|
||||
do_nothing = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
bool scheduler_srcs_ready = true;
|
||||
if (inst_in_scheduler.rs1 > 0)
|
||||
{
|
||||
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs1];
|
||||
// cout << "Rename RS1: " << inst_in_scheduler.rs1 << " is " << renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs1] << " wid: " << inst_in_scheduler.wid << '\n';
|
||||
}
|
||||
|
||||
if (inst_in_scheduler.rs2 > 0)
|
||||
{
|
||||
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2];
|
||||
// cout << "Rename RS2: " << inst_in_scheduler.rs1 << " is " << renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2] << " wid: " << inst_in_scheduler.wid << '\n';
|
||||
}
|
||||
|
||||
if (scheduler_srcs_ready)
|
||||
{
|
||||
if (inst_in_scheduler.rd != -1) {
|
||||
// cout << "rename setting rd: " << inst_in_scheduler.rd << " to not useabel wid: " << inst_in_scheduler.wid << '\n';
|
||||
renameTable[inst_in_scheduler.wid][inst_in_scheduler.rd] = false;
|
||||
}
|
||||
CPY_TRACE(inst_in_exe, inst_in_scheduler);
|
||||
INIT_TRACE(inst_in_scheduler);
|
||||
}
|
||||
else
|
||||
{
|
||||
cout << "&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY\n";
|
||||
inst_in_scheduler.stalled = true;
|
||||
// INIT_TRACE(inst_in_exe);
|
||||
do_nothing = true;
|
||||
}
|
||||
}
|
||||
|
||||
// if (!do_nothing)
|
||||
// {
|
||||
|
||||
// }
|
||||
|
||||
printTrace(&inst_in_exe, "execute_unit");
|
||||
// INIT_TRACE(inst_in_exe);
|
||||
}
|
||||
|
||||
void Core::writeback()
|
||||
{
|
||||
|
||||
|
||||
if (inst_in_wb.rd > 0) renameTable[inst_in_wb.wid][inst_in_wb.rd] = true;
|
||||
|
||||
if (inst_in_wb.stall_warp)
|
||||
{
|
||||
// stallWarp[inst_in_wb.wid] = false;
|
||||
release_warp = true;
|
||||
release_warp_num = inst_in_wb.wid;
|
||||
}
|
||||
|
||||
|
||||
INIT_TRACE(inst_in_wb);
|
||||
|
||||
bool serviced_exe = false;
|
||||
bool serviced_mem = false;
|
||||
if ((inst_in_exe.rd > 0) || (inst_in_exe.stall_warp))
|
||||
{
|
||||
CPY_TRACE(inst_in_wb, inst_in_exe);
|
||||
INIT_TRACE(inst_in_exe);
|
||||
|
||||
serviced_exe = true;
|
||||
// cout << "WRITEBACK SERVICED EXE\n";
|
||||
}
|
||||
|
||||
if ((inst_in_lsu.rd > 0) && (inst_in_lsu.mem_stall_cycles == 0))
|
||||
{
|
||||
if (serviced_exe)
|
||||
{
|
||||
cout << "$$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used\n";
|
||||
inst_in_lsu.stalled = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
serviced_mem = true;
|
||||
CPY_TRACE(inst_in_wb, inst_in_lsu);
|
||||
INIT_TRACE(inst_in_lsu);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
// if (!serviced_exe && !serviced_mem) INIT_TRACE(inst_in_wb);
|
||||
|
||||
printTrace(&inst_in_wb, "Writeback");
|
||||
|
||||
}
|
||||
|
||||
|
||||
bool Core::running() const {
|
||||
bool stages_have_valid = inst_in_fetch.valid_inst || inst_in_decode.valid_inst || inst_in_scheduler.valid_inst ||
|
||||
inst_in_lsu.valid_inst || inst_in_exe.valid_inst || inst_in_wb.valid_inst;
|
||||
|
||||
if (stages_have_valid) return true;
|
||||
|
||||
for (unsigned i = 0; i < w.size(); ++i)
|
||||
if (w[i].running()) return true;
|
||||
if (w[i].running())
|
||||
{
|
||||
cout << "Warp ID " << i << " is running\n";
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -140,8 +623,7 @@ void Core::printStats() const {
|
|||
for (unsigned i = 0; i < w.size(); ++i)
|
||||
insts += w[i].insts;
|
||||
|
||||
cout << "Total steps: " << steps << endl;
|
||||
cout << "Total insts: " << insts << endl;
|
||||
cerr << "Total steps: " << steps << endl;
|
||||
for (unsigned i = 0; i < w.size(); ++i) {
|
||||
cout << "=== Warp " << i << " ===" << endl;
|
||||
w[i].printStats();
|
||||
|
|
@ -190,7 +672,7 @@ void Warp::step(trace_inst_t * trace_inst) {
|
|||
|
||||
if (activeThreads == 0) return;
|
||||
|
||||
++steps;
|
||||
// ++steps;
|
||||
|
||||
D(3, "in step pc=0x" << hex << pc);
|
||||
|
||||
|
|
@ -219,7 +701,7 @@ void Warp::step(trace_inst_t * trace_inst) {
|
|||
|
||||
// Execute
|
||||
|
||||
inst->executeOn(*this);
|
||||
inst->executeOn(*this, trace_inst);
|
||||
|
||||
|
||||
// At Debug Level 3, print debug info after each instruction.
|
||||
|
|
@ -274,13 +756,13 @@ bool Warp::interrupt(Word r0) {
|
|||
}
|
||||
|
||||
void Warp::printStats() const {
|
||||
cerr << "Steps : " << steps << endl
|
||||
cout << "Steps : " << steps << endl
|
||||
<< "Insts : " << insts << endl
|
||||
<< "Loads : " << loads << endl
|
||||
<< "Stores: " << stores << endl;
|
||||
|
||||
unsigned const grade = reg[0][28];
|
||||
|
||||
if (grade == 1) cerr << "GRADE: PASSED\n";
|
||||
else cerr << "GRADE: FAILED " << (grade >> 1) << "\n";
|
||||
if (grade == 1) cout << "GRADE: PASSED\n";
|
||||
else cout << "GRADE: FAILED " << (grade >> 1) << "\n";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,9 +19,9 @@
|
|||
#include "Vcache_simX.h"
|
||||
#include "verilated.h"
|
||||
|
||||
#ifdef VCD_OUTPUT
|
||||
// #ifdef VCD_OUTPUT
|
||||
#include <verilated_vcd_c.h>
|
||||
#endif
|
||||
// #endif
|
||||
|
||||
|
||||
#include "trace.h"
|
||||
|
|
@ -92,17 +92,34 @@ namespace Harp {
|
|||
public:
|
||||
Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id=0);
|
||||
|
||||
Vcache_simX * cache_simulator;
|
||||
Vcache_simX * cache_simulator;
|
||||
VerilatedVcdC * m_trace;
|
||||
|
||||
bool renameTable[32][32];
|
||||
bool stallWarp[32];
|
||||
bool foundSchedule;
|
||||
|
||||
trace_inst_t inst_in_fetch;
|
||||
trace_inst_t inst_in_decode;
|
||||
trace_inst_t inst_in_scheduler;
|
||||
trace_inst_t inst_in_exe;
|
||||
trace_inst_t inst_in_lsu;
|
||||
trace_inst_t inst_in_wb;
|
||||
|
||||
bool release_warp;
|
||||
int release_warp_num;
|
||||
|
||||
bool interrupt(Word r0);
|
||||
bool running() const;
|
||||
|
||||
void getCacheDelays(trace_inst_t *);
|
||||
void warpScheduler();
|
||||
void fetch();
|
||||
void decode();
|
||||
void scheduler();
|
||||
void gpr_read();
|
||||
void execute_unit();
|
||||
void load_store();
|
||||
void writeback();
|
||||
|
||||
void step();
|
||||
|
||||
|
|
@ -117,6 +134,7 @@ namespace Harp {
|
|||
unsigned long steps;
|
||||
std::vector<Warp> w;
|
||||
std::map<Word, std::set<Warp *> > b; // Barriers
|
||||
int schedule_w;
|
||||
};
|
||||
|
||||
class Warp {
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#include <iostream>
|
||||
|
||||
#include "types.h"
|
||||
|
||||
#include "trace.h"
|
||||
namespace Harp {
|
||||
class Warp;
|
||||
class Ref;
|
||||
|
|
@ -79,7 +79,7 @@ namespace Harp {
|
|||
{
|
||||
}
|
||||
|
||||
void executeOn(Warp &warp);
|
||||
void executeOn(Warp &warp, trace_inst_t *);
|
||||
friend std::ostream &operator<<(std::ostream &, Instruction &);
|
||||
|
||||
/* Setters used to "craft" the instruction. */
|
||||
|
|
|
|||
|
|
@ -28,6 +28,9 @@ namespace Harp {
|
|||
|
||||
// Instruction execute
|
||||
bool stall_warp;
|
||||
bool wspawn;
|
||||
|
||||
bool stalled;
|
||||
} trace_inst_t;
|
||||
|
||||
}
|
||||
|
|
@ -78,7 +78,7 @@ Word signExt(Word w, Size bit, Word mask) {
|
|||
return w;
|
||||
}
|
||||
|
||||
void Instruction::executeOn(Warp &c) {
|
||||
void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
|
||||
D(3, "Begin instruction execute.");
|
||||
|
||||
/* If I try to execute a privileged instruction in user mode, throw an
|
||||
|
|
@ -357,14 +357,14 @@ void Instruction::executeOn(Warp &c) {
|
|||
break;
|
||||
case L_INST:
|
||||
//std::cout << "L_INST\n";
|
||||
|
||||
memAddr = ((reg[rsrc[0]] + immsrc) & 0xFFFFFFFC);
|
||||
shift_by = ((reg[rsrc[0]] + immsrc) & 0x00000003) * 8;
|
||||
data_read = c.core->mem.read(memAddr, c.supervisorMode);
|
||||
trace_inst->is_lw = true;
|
||||
trace_inst->mem_addresses[t] = memAddr;
|
||||
// //std::cout <<std::hex<< "EXECUTE: " << reg[rsrc[0]] << " + " << immsrc << " = " << memAddr << " -> data_read: " << data_read << "\n";
|
||||
#ifdef EMU_INSTRUMENTATION
|
||||
Harp::OSDomain::osDomain->
|
||||
do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
|
||||
#endif
|
||||
|
||||
switch (func3)
|
||||
{
|
||||
|
||||
|
|
@ -484,6 +484,8 @@ void Instruction::executeOn(Warp &c) {
|
|||
++c.stores;
|
||||
memAddr = reg[rsrc[0]] + immsrc;
|
||||
std::cout << "STORE MEM ADDRESS: " << std::hex << reg[rsrc[0]] << " + " << immsrc << "\n";
|
||||
trace_inst->is_sw = true;
|
||||
trace_inst->mem_addresses[t] = memAddr;
|
||||
// //std::cout << "FUNC3: " << func3 << "\n";
|
||||
if ((memAddr == 0x00010000) && (t == 0))
|
||||
{
|
||||
|
|
@ -517,6 +519,7 @@ void Instruction::executeOn(Warp &c) {
|
|||
break;
|
||||
case B_INST:
|
||||
//std::cout << "B_INST\n";
|
||||
trace_inst->stall_warp = true;
|
||||
switch (func3)
|
||||
{
|
||||
case 0:
|
||||
|
|
@ -579,6 +582,7 @@ void Instruction::executeOn(Warp &c) {
|
|||
break;
|
||||
case JAL_INST:
|
||||
//std::cout << "JAL_INST\n";
|
||||
trace_inst->stall_warp = true;
|
||||
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
|
||||
if (!pcSet) {/*std::cout << "JAL... SETTING PC: " << nextPc << "\n"; */}
|
||||
if (rdest != 0)
|
||||
|
|
@ -589,6 +593,7 @@ void Instruction::executeOn(Warp &c) {
|
|||
break;
|
||||
case JALR_INST:
|
||||
std::cout << "JALR_INST\n";
|
||||
trace_inst->stall_warp = true;
|
||||
if (!pcSet) nextPc = reg[rsrc[0]] + immsrc;
|
||||
if (!pcSet) {/*std::cout << "JALR... SETTING PC: " << nextPc << "\n";*/ }
|
||||
if (rdest != 0)
|
||||
|
|
@ -704,6 +709,7 @@ void Instruction::executeOn(Warp &c) {
|
|||
case 1:
|
||||
// WSPAWN
|
||||
std::cout << "WSPAWN\n";
|
||||
trace_inst->wspawn = true;
|
||||
if (sjOnce)
|
||||
{
|
||||
sjOnce = false;
|
||||
|
|
@ -745,6 +751,7 @@ void Instruction::executeOn(Warp &c) {
|
|||
{
|
||||
// SPLIT
|
||||
//std::cout << "SPLIT\n";
|
||||
trace_inst->stall_warp = true;
|
||||
if (sjOnce)
|
||||
{
|
||||
sjOnce = false;
|
||||
|
|
@ -812,12 +819,13 @@ void Instruction::executeOn(Warp &c) {
|
|||
}
|
||||
break;
|
||||
case 4:
|
||||
trace_inst->stall_warp = true;
|
||||
// is_barrier
|
||||
break;
|
||||
case 0:
|
||||
// TMC
|
||||
//std::cout << "JALRS\n";
|
||||
|
||||
trace_inst->stall_warp = true;
|
||||
nextActiveThreads = reg[rsrc[0]];
|
||||
{
|
||||
for (int ff = 0; ff < c.tmask.size(); ff++)
|
||||
|
|
|
|||
|
|
@ -104,6 +104,24 @@ int emu_main(int argc, char **argv) {
|
|||
|
||||
// core.w[0].pc = 0x8000007c; // If I want to start at a specific location
|
||||
std::cout << "ABOUT TO START\n";
|
||||
// bool count_down = false;
|
||||
// int cycles_left;
|
||||
// while (!count_down || (count_down && (cycles_left == 0)))
|
||||
// {
|
||||
|
||||
// if (count_down)
|
||||
// {
|
||||
// cycles_left--;
|
||||
// }
|
||||
|
||||
// console.poll();
|
||||
// core.step();
|
||||
// bool run = core.running();
|
||||
// if (!run)
|
||||
// {
|
||||
// count_down = true;
|
||||
// }
|
||||
// }
|
||||
while (core.running()) { console.poll(); core.step(); }
|
||||
|
||||
if (showStats) core.printStats();
|
||||
|
|
|
|||
|
|
@ -3,4 +3,5 @@ echo start > results.txt
|
|||
# echo ../kernel/vortex_test.hex
|
||||
make clean
|
||||
make
|
||||
echo "Fasten your seatbelts ladies and gentelmen!!"
|
||||
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/dev/vx_dev_main.hex -s -b 1> emulator.debug
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue