mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
Replaced instruction information arrays with a table.
git-svn-id: http://www.cdkersey.com/harp/harptool@12 0246edb2-e076-4747-b392-db732a341fa2
This commit is contained in:
chad
parent
600d27ec60
commit
f758375767
4 changed files with 79 additions and 74 deletions
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@ -109,7 +109,7 @@ Instruction *ByteDecoder::decode(const vector<Byte> &v, Size &n) {
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bool usedImm = false;
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switch (Instruction::argClasses[op]) {
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switch (Instruction::instTable[op].argClass) {
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case Instruction::AC_NONE:
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break;
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case Instruction::AC_2REG:
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@ -276,7 +276,7 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx) {
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inst.setOpcode(op);
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bool usedImm(false);
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switch(Instruction::argClasses[op]) {
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switch(Instruction::instTable[op].argClass) {
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case Instruction::AC_NONE:
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break;
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case Instruction::AC_1IMM:
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@ -35,9 +35,13 @@ namespace Harp {
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AC_NONE, AC_2REG, AC_2IMM, AC_3REG, AC_3PREG, AC_3IMM, AC_3REGSRC,
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AC_1IMM, AC_1REG, AC_3IMMSRC, AC_PREG_REG, AC_2PREG
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};
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static const char *opStrings[];
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static const bool allSrcArgs[], privileged[], relAddress[], isControlFlow[];
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static const ArgClass argClasses[];
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// We build a table of instruction information out of this.
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static struct InstTableEntry {
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const char *opString;
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bool controlFlow, relAddress, allSrcArgs, privileged;
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ArgClass argClass;
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} instTable[];
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Instruction() :
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predicated(false), nRsrc(0), nPsrc(0), immsrcPresent(false),
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@ -75,7 +79,7 @@ namespace Harp {
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Ref *getRefLiteral() const { return refLiteral; }
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/* Getters used as table lookup. */
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bool hasRelImm() const { return relAddress[op]; }
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bool hasRelImm() const { return instTable[op].relAddress; }
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private:
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bool predicated;
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@ -14,68 +14,68 @@ using namespace std;
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/* It is important that this stays consistent with the Harp::Instruction::Opcode
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enum. */
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const char *Instruction::opStrings[] = {
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"nop", "di", "ei", "tlbadd", "tlbflush", "neg", "not", "and", "or", "xor",
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"add", "sub", "mul", "div", "mod", "shl", "shr","andi",
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"ori", "xori", "addi", "subi", "muli", "divi", "modi", "shli", "shri",
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"jali", "jalr", "jmpi", "jmpr", "clone", "jalis", "jalrs",
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"jmprt", "ld", "st", "ldi", "rtop", "andp", "orp", "xorp", "notp",
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"isneg", "iszero", "halt", "trap", "jmpru", "skep", "reti", "tlbrm",
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"itof", "ftoi", "fadd", "fsub", "fmul", "fdiv", "fneg", 0
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};
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const bool Instruction::isControlFlow[] = {
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false, false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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true, true, true, true, true, true, true,
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true, false, false, false, false, false, false, false, false,
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false, false, false, false, true, false, true, false,
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false, false, false, false, false, false, false
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};
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const bool Instruction::relAddress[] = {
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false, false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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true, false, true, false, false, true, false,
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false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false
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};
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const bool Instruction::allSrcArgs[] = {
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false, false, false, true, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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false, false, true, true, false, false, false,
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true, false, true, false, false, false, false, false, false,
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false, false, false, false, true, true, false, false,
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false, false, false, false, false, false, false
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};
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const bool Instruction::privileged[] = {
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false, true, true, true, true, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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false, false, true, false, true, true, true, true,
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false, false, false, false, false, false, false
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};
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const Instruction::ArgClass Instruction::argClasses[] = {
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AC_NONE, AC_NONE, AC_NONE, AC_3REGSRC, AC_NONE, AC_2REG, AC_2REG, AC_3REG,
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AC_3REG, AC_3REG,
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AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3IMM,
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AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM,
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AC_3IMM,
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AC_2IMM, AC_2REG, AC_1IMM, AC_1REG, AC_1REG, AC_3IMM, AC_3REG,
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AC_1REG, AC_3IMM, AC_3IMMSRC, AC_2IMM, AC_PREG_REG, AC_3PREG, AC_3PREG,
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AC_3PREG, AC_2PREG,
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AC_PREG_REG, AC_PREG_REG, AC_NONE, AC_NONE, AC_1REG, AC_1REG, AC_NONE,
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AC_1REG,
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AC_2REG, AC_2REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_2REG
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Instruction::InstTableEntry Instruction::instTable[] = {
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//str cflow relad allsrc priv argcl
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{"nop", false, false, false, false, AC_NONE },
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{"di", false, false, false, true, AC_NONE },
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{"ei", false, false, false, true, AC_NONE },
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{"tlbadd", false, false, true, true, AC_3REGSRC },
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{"tlbflush", false, false, false, true, AC_NONE },
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{"neg", false, false, false, false, AC_2REG },
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{"not", false, false, false, false, AC_2REG },
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{"and", false, false, false, false, AC_3REG },
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{"or", false, false, false, false, AC_3REG },
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{"xor", false, false, false, false, AC_3REG },
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{"add", false, false, false, false, AC_3REG },
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{"sub", false, false, false, false, AC_3REG },
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{"mul", false, false, false, false, AC_3REG },
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{"div", false, false, false, false, AC_3REG },
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{"mod", false, false, false, false, AC_3REG },
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{"shl", false, false, false, false, AC_3REG },
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{"shr", false, false, false, false, AC_3REG },
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{"andi", false, false, false, false, AC_3IMM },
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{"ori", false, false, false, false, AC_3IMM },
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{"xori", false, false, false, false, AC_3IMM },
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{"addi", false, false, false, false, AC_3IMM },
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{"subi", false, false, false, false, AC_3IMM },
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{"muli", false, false, false, false, AC_3IMM },
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{"divi", false, false, false, false, AC_3IMM },
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{"modi", false, false, false, false, AC_3IMM },
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{"shli", false, false, false, false, AC_3IMM },
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{"shri", false, false, false, false, AC_3IMM },
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{"jali", true, true, false, false, AC_2IMM },
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{"jalr", true, false, false, false, AC_2REG },
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{"jmpi", true, true, true, false, AC_1IMM },
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{"jmpr", true, false, true, false, AC_1REG },
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{"clone", true, false, false, false, AC_1REG },
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{"jalis", true, true, false, false, AC_3IMM },
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{"jalrs", true, false, false, false, AC_3REG },
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{"jmprt", true, false, true, false, AC_1REG },
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{"ld", false, false, false, false, AC_3IMM },
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{"st", false, false, true, false, AC_3IMMSRC },
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{"ldi", false, false, false, false, AC_2IMM },
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{"rtop", false, false, false, false, AC_PREG_REG},
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{"andp", false, false, false, false, AC_3PREG },
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{"orp", false, false, false, false, AC_3PREG },
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{"xorp", false, false, false, false, AC_3PREG },
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{"notp", false, false, false, false, AC_3PREG },
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{"isneg", false, false, false, false, AC_PREG_REG},
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{"iszero", false, false, false, false, AC_PREG_REG},
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{"halt", false, false, false, true, AC_NONE },
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{"trap", true, false, false, false, AC_NONE },
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{"jmpru", false, false, false, true, AC_1REG },
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{"skep", false, false, false, true, AC_1REG },
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{"reti", true, false, false, true, AC_NONE },
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{"tlbrm", false, false, false, true, AC_1REG },
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{"itof", false, false, false, false, AC_2REG },
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{"ftoi", false, false, false, false, AC_2REG },
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{"fadd", false, false, false, false, AC_3REG },
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{"fsub", false, false, false, false, AC_3REG },
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{"fmul", false, false, false, false, AC_3REG },
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{"fdiv", false, false, false, false, AC_3REG },
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{"fneg", false, false, false, false, AC_2REG },
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{NULL,false,false,false,false,AC_NONE}/////////////// End of table.
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};
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ostream &Harp::operator<<(ostream& os, Instruction &inst) {
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@ -83,7 +83,7 @@ ostream &Harp::operator<<(ostream& os, Instruction &inst) {
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os << "@p" << inst.pred << " ? ";
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}
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os << Instruction::opStrings[inst.op] << ' ';
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os << Instruction::instTable[inst.op].opString << ' ';
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if (inst.rdestPresent) os << "%r" << inst.rdest << ' ';
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if (inst.pdestPresent) os << "@p" << inst.pdest << ' ';
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for (int i = 0; i < inst.nRsrc; i++) {
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@ -104,12 +104,12 @@ ostream &Harp::operator<<(ostream& os, Instruction &inst) {
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void Instruction::executeOn(Core &c) {
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/* If I try to execute a privileged instruction in user mode, throw an
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exception 3. */
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if (privileged[op] && !c.supervisorMode) {
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if (instTable[op].privileged && !c.supervisorMode) {
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c.interrupt(3);
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return;
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}
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if (predicated && isControlFlow[op]) {
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if (predicated && instTable[op].controlFlow) {
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bool p0 = c.pred[0][pred];
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for (Size t = 1; t < c.activeThreads; t++) {
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if (c.pred[t][pred] != p0) throw DivergentBranchException();
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@ -244,7 +244,7 @@ void Instruction::executeOn(Core &c) {
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exit(1);
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}
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if (isControlFlow[op]) break;
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if (instTable[op].controlFlow) break;
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}
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c.activeThreads = nextActiveThreads;
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@ -104,8 +104,9 @@ Obj *AsmReader::read(std::istream &input) {
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map <string, Instruction::Opcode> opMap;
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// Build opMap
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for (size_t i = 0; Instruction::opStrings[i]; i++)
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opMap[std::string(Instruction::opStrings[i])] = Instruction::Opcode(i);
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for (size_t i = 0; Instruction::instTable[i].opString; i++)
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opMap[std::string(Instruction::instTable[i].opString)]
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= Instruction::Opcode(i);
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enum {
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ST_INIT, ST_DEF1, ST_DEF2, ST_PERM, ST_WORD1, ST_WORD2, ST_STRING1,
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@ -316,7 +317,7 @@ Obj *AsmReader::read(std::istream &input) {
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nextPred = false;
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curInst->setPred(nextPredNum);
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}
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state = Instruction::allSrcArgs[opc]?ST_INST2:ST_INST1;
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state = Instruction::instTable[opc].allSrcArgs?ST_INST2:ST_INST1;
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} else { asmReaderError(yyline, "Unexpected token"); }
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break;
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case ASM_T_PREG:
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