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minor update

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Blaise Tine 2024-02-12 04:19:31 -08:00
parent 21b54761e3
commit f83094e0d9
2 changed files with 5 additions and 8 deletions
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8
hw/rtl/cache/VX_cache_bypass.sv vendored
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@ -358,14 +358,12 @@ module VX_cache_bypass #(
.data_out (mem_bus_in_if.rsp_data.tag)
);
wire [NUM_REQS-1:0] core_rsp_valid_in;
wire [NUM_REQS-1:0] core_rsp_ready_out;
wire [NUM_REQS-1:0] core_rsp_out_valid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_rsp_valid_in[i] = core_bus_out_if[i].rsp_valid;
assign core_rsp_ready_out[i] = core_bus_in_if[i].rsp_ready;
assign core_rsp_out_valid[i] = core_bus_out_if[i].rsp_valid;
end
assign mem_bus_out_if.rsp_ready = is_mem_rsp_nc ? (~core_rsp_valid_in[rsp_idx] && core_rsp_ready_out[rsp_idx]) : mem_bus_in_if.rsp_ready;
assign mem_bus_out_if.rsp_ready = is_mem_rsp_nc ? (~core_rsp_out_valid[rsp_idx] && core_rsp_in_ready[rsp_idx]) : mem_bus_in_if.rsp_ready;
endmodule

5
hw/rtl/core/VX_commit.sv
View file

@ -49,10 +49,9 @@ module VX_commit import VX_gpu_pkg::*; #(
wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] commit_tmask;
wire [`ISSUE_WIDTH-1:0] commit_eop;
`RESET_RELAY (arb_reset, reset);
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
`RESET_RELAY (arb_reset, reset);
VX_stream_arb #(
.NUM_INPUTS (`NUM_EX_UNITS),
.DATAW (DATAW),