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riscv tests refactoring

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Blaise Tine 2024-05-28 10:46:31 -07:00
parent 0426856ab4
commit f8ef570778
1140 changed files with 574 additions and 160937 deletions
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17
sim/rtlsim/main.cpp
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@ -95,21 +95,10 @@ int main(int argc, char **argv) {
}
// run simulation
exitcode = processor.run();
processor.run();
if (riscv_test) {
if (1 == exitcode) {
std::cout << "Passed" << std::endl;
exitcode = 0;
} else {
std::cout << "Failed" << std::endl;
exitcode = 1;
}
} else {
if (exitcode != 0) {
std::cout << "*** error: exitcode=" << exitcode << std::endl;
}
}
// read exitcode from @MPM.1
ram.read(&exitcode, (IO_MPM_ADDR + 8), 4);
return exitcode;
}