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minor update

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This commit is contained in:
Blaise Tine 2024-09-03 06:14:09 -07:00
parent 19d6142023
commit f9230bdac3
5 changed files with 33 additions and 22 deletions
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5
hw/rtl/fpu/VX_fpu_cvt.sv
View file

@ -49,6 +49,7 @@ module VX_fpu_cvt import VX_fpu_pkg::*; #(
localparam DATAW = 32 + `INST_FRM_BITS + 1 + 1;
wire [NUM_LANES-1:0][DATAW-1:0] data_in;
wire [NUM_LANES-1:0] mask_out;
wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out;
fflags_t [NUM_LANES-1:0] fflags_out;
@ -68,8 +69,8 @@ module VX_fpu_cvt import VX_fpu_pkg::*; #(
.NUM_LANES (NUM_LANES),
.NUM_PES (NUM_PES),
.LATENCY (`LATENCY_FCVT),
.DATA_IN_WIDTH(DATAW),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.DATA_IN_WIDTH (DATAW),
.DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG (0),
.OUT_BUF (2)

18
hw/rtl/fpu/VX_fpu_div.sv
View file

@ -44,11 +44,10 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
output wire valid_out,
input wire ready_out
);
`UNUSED_VAR (frm)
localparam DATAW = 2 * 32;
localparam DATAW = 2 * 32 + `INST_FRM_BITS;
wire [NUM_LANES-1:0][DATAW-1:0] data_in;
wire [NUM_LANES-1:0] mask_out;
wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out;
wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out;
@ -60,14 +59,15 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign data_in[i][0 +: 32] = dataa[i];
assign data_in[i][32 +: 32] = datab[i];
assign data_in[i][64 +: `INST_FRM_BITS] = frm;
end
VX_pe_serializer #(
.NUM_LANES (NUM_LANES),
.NUM_PES (NUM_PES),
.LATENCY (`LATENCY_FDIV),
.DATA_IN_WIDTH(DATAW),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.DATA_IN_WIDTH (DATAW),
.DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG (0),
.OUT_BUF (2)
@ -87,6 +87,8 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
.ready_out (ready_out)
);
`UNUSED_VAR (pe_data_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign result[i] = data_out[i][0 +: 32];
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
@ -145,9 +147,9 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
dpi_fdiv (
pe_enable,
int'(0),
{32'hffffffff, pe_data_in[i][0 +: 32]},
{32'hffffffff, pe_data_in[i][32 +: 32]},
frm,
{32'hffffffff, pe_data_in[i][0 +: 32]}, // a
{32'hffffffff, pe_data_in[i][32 +: 32]}, // b
pe_data_in[0][64 +: `INST_FRM_BITS], // frm
r,
f
);

5
hw/rtl/fpu/VX_fpu_fma.sv
View file

@ -52,6 +52,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
localparam DATAW = 3 * 32 + `INST_FRM_BITS;
wire [NUM_LANES-1:0][DATAW-1:0] data_in;
wire [NUM_LANES-1:0] mask_out;
wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out;
wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out;
@ -96,8 +97,8 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
.NUM_LANES (NUM_LANES),
.NUM_PES (NUM_PES),
.LATENCY (`LATENCY_FMA),
.DATA_IN_WIDTH(DATAW),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.DATA_IN_WIDTH (DATAW),
.DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG (1), // must be registered for DSPs
.OUT_BUF (2)

5
hw/rtl/fpu/VX_fpu_ncp.sv
View file

@ -48,6 +48,7 @@ module VX_fpu_ncp import VX_fpu_pkg::*; #(
localparam DATAW = 2 * 32 + `INST_FRM_BITS + `INST_FPU_BITS;
wire [NUM_LANES-1:0][DATAW-1:0] data_in;
wire [NUM_LANES-1:0] mask_out;
wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out;
fflags_t [NUM_LANES-1:0] fflags_out;
@ -67,8 +68,8 @@ module VX_fpu_ncp import VX_fpu_pkg::*; #(
.NUM_LANES (NUM_LANES),
.NUM_PES (NUM_PES),
.LATENCY (`LATENCY_FNCP),
.DATA_IN_WIDTH(DATAW),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.DATA_IN_WIDTH (DATAW),
.DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG (0),
.OUT_BUF (2)

22
hw/rtl/fpu/VX_fpu_sqrt.sv
View file

@ -43,10 +43,9 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
input wire ready_out,
output wire valid_out
);
localparam DATAW = 32 + `INST_FRM_BITS;
`UNUSED_VAR (frm)
localparam DATAW = 32;
wire [NUM_LANES-1:0][DATAW-1:0] data_in;
wire [NUM_LANES-1:0] mask_out;
wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out;
@ -56,12 +55,17 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
wire [NUM_PES-1:0][DATAW-1:0] pe_data_in;
wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign data_in[i][0 +: 32] = dataa[i];
assign data_in[i][32 +: `INST_FRM_BITS] = frm;
end
VX_pe_serializer #(
.NUM_LANES (NUM_LANES),
.NUM_PES (NUM_PES),
.LATENCY (`LATENCY_FSQRT),
.DATA_IN_WIDTH(DATAW),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.DATA_IN_WIDTH (DATAW),
.DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG (0),
.OUT_BUF (2)
@ -69,7 +73,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.data_in (dataa),
.data_in (data_in),
.tag_in ({mask_in, tag_in}),
.ready_in (ready_in),
.pe_enable (pe_enable),
@ -81,6 +85,8 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
.ready_out (ready_out)
);
`UNUSED_VAR (pe_data_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign result[i] = data_out[i][0 +: 32];
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
@ -137,8 +143,8 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
dpi_fsqrt (
pe_enable,
int'(0),
{32'hffffffff, pe_data_in[i]},
frm,
{32'hffffffff, pe_data_in[i][0 +: 32]}, // a
pe_data_in[0][32 +: `INST_FRM_BITS], // frm
r,
f
);