mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
Minor update
This commit is contained in:
Santosh Srivatsan
parent
71acf4eadb
commit
f93303bac7
5 changed files with 66 additions and 114 deletions
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@ -41,131 +41,131 @@ extern "C" {
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void dpi_fadd(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fadd(a, b, (*frm & 0x7), fflags);
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*result = rv_fadd_s(a, b, (*frm & 0x7), fflags);
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}
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void dpi_fsub(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fsub(a, b, (*frm & 0x7), fflags);
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*result = rv_fsub_s(a, b, (*frm & 0x7), fflags);
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}
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void dpi_fmul(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fmul(a, b, (*frm & 0x7), fflags);
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*result = rv_fmul_s(a, b, (*frm & 0x7), fflags);
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}
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void dpi_fmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fmadd(a, b, c, (*frm & 0x7), fflags);
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*result = rv_fmadd_s(a, b, c, (*frm & 0x7), fflags);
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}
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void dpi_fmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fmsub(a, b, c, (*frm & 0x7), fflags);
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*result = rv_fmsub_s(a, b, c, (*frm & 0x7), fflags);
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}
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void dpi_fnmadd(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fnmadd(a, b, c, (*frm & 0x7), fflags);
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*result = rv_fnmadd_s(a, b, c, (*frm & 0x7), fflags);
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}
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void dpi_fnmsub(bool enable, int a, int b, int c, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fnmsub(a, b, c, (*frm & 0x7), fflags);
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*result = rv_fnmsub_s(a, b, c, (*frm & 0x7), fflags);
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}
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void dpi_fdiv(bool enable, int a, int b, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fdiv(a, b, (*frm & 0x7), fflags);
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*result = rv_fdiv_s(a, b, (*frm & 0x7), fflags);
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}
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void dpi_fsqrt(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fsqrt(a, (*frm & 0x7), fflags);
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*result = rv_fsqrt_s(a, (*frm & 0x7), fflags);
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}
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void dpi_ftoi(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_ftoi(a, (*frm & 0x7), fflags);
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*result = rv_ftoi_s(a, (*frm & 0x7), fflags);
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}
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void dpi_ftou(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_ftou(a, (*frm & 0x7), fflags);
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*result = rv_ftou_s(a, (*frm & 0x7), fflags);
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}
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void dpi_itof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_itof(a, (*frm & 0x7), fflags);
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*result = rv_itof_s(a, (*frm & 0x7), fflags);
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}
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void dpi_utof(bool enable, int a, const svBitVecVal* frm, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_utof(a, (*frm & 0x7), fflags);
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*result = rv_utof_s(a, (*frm & 0x7), fflags);
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}
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void dpi_flt(bool enable, int a, int b, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_flt(a, b, fflags);
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*result = rv_flt_s(a, b, fflags);
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}
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void dpi_fle(bool enable, int a, int b, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fle(a, b, fflags);
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*result = rv_fle_s(a, b, fflags);
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}
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void dpi_feq(bool enable, int a, int b, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_feq(a, b, fflags);
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*result = rv_feq_s(a, b, fflags);
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}
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void dpi_fmin(bool enable, int a, int b, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fmin(a, b, fflags);
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*result = rv_fmin_s(a, b, fflags);
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}
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void dpi_fmax(bool enable, int a, int b, int* result, svBitVecVal* fflags) {
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if (!enable)
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return;
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*result = rv_fmax(a, b, fflags);
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*result = rv_fmax_s(a, b, fflags);
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}
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void dpi_fclss(bool enable, int a, int* result) {
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if (!enable)
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return;
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*result = rv_fclss(a);
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*result = rv_fclss_s(a);
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}
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void dpi_fsgnj(bool enable, int a, int b, int* result) {
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if (!enable)
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return;
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*result = rv_fsgnj(a, b);
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*result = rv_fsgnj_s(a, b);
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}
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void dpi_fsgnjn(bool enable, int a, int b, int* result) {
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if (!enable)
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return;
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*result = rv_fsgnjn(a, b);
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*result = rv_fsgnjn_s(a, b);
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}
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void dpi_fsgnjx(bool enable, int a, int b, int* result) {
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if (!enable)
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return;
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*result = rv_fsgnjx(a, b);
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*result = rv_fsgnjx_s(a, b);
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}
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@ -1,48 +0,0 @@
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# Dockerfile for setting up the vortex development environment
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FROM ubuntu:18.04
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# Install dependencies
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RUN apt update && apt install -y \
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git build-essential g++ libfl2 \
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libfl-dev zlibc zlib1g zlib1g-dev \
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ccache libgoogle-perftools-dev numactl perl-doc \
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python3 device-tree-compiler gdb
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# Download vortex-toolchain-prebuilt
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RUN git clone https://github.com/SantoshSrivatsan24/vortex-toolchain-prebuilt.git /tmp/vortex-toolchain-prebuilt
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# Copy riscv-gnu-toolchain
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RUN cd /tmp/vortex-toolchain-prebuilt/riscv-gnu-toolchain/ubuntu/bionic; \
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cat riscv-gnu-toolchain.tar.bz2.part* > riscv-gnu-toolchain.tar.bz2; \
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tar -xf riscv-gnu-toolchain.tar.bz2 -C /opt/;
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# Copy riscv64-gnu-toolchain
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RUN cd /tmp/vortex-toolchain-prebuilt/riscv64-gnu-toolchain/ubuntu/bionic; \
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cat riscv64-gnu-toolchain.tar.bz2.part* > riscv64-gnu-toolchain.tar.bz2; \
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tar -xf riscv64-gnu-toolchain.tar.bz2 -C /opt/;
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# Copy llvm-riscv
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RUN cd /tmp/vortex-toolchain-prebuilt/llvm-riscv/ubuntu/bionic; \
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cat llvm-riscv.tar.bz2.part* > llvm-riscv.tar.bz2; \
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tar -xf llvm-riscv.tar.bz2 -C /opt/;
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# Copy pocl
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RUN cd /tmp/vortex-toolchain-prebuilt/pocl/ubuntu/bionic; \
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tar -xf pocl.tar.bz2 -C /opt/;
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# Copy verilator
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RUN cd /tmp/vortex-toolchain-prebuilt/verilator/ubuntu/bionic; \
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tar -xf verilator.tar.bz2 -C /opt/;
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# Set environment variables
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ENV RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain
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ENV RISCV64_TOOLCHAIN_PATH=/opt/riscv64-gnu-toolchain
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ENV VERILATOR_ROOT=/opt/verilator
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ENV PATH=$PATH:/${RISCV_TOOLCHAIN_PATH}/bin:${RISCV64_TOOLCHAIN_PATH}/bin:${RISCV64_TOOLCHAIN_PATH}/riscv64-unknown-elf/bin:${VERILATOR_ROOT}/bin
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# Cleanup
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RUN rm -rf /tmp/vortex-toolchain-prebuilt
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# Set working directory
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WORKDIR /home/vortex
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@ -82,8 +82,8 @@ inline uint64_t sext64(uint64_t word, uint64_t width) {
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assert(width > 1);
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assert(width <= 64);
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uint64_t unity = 1;
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uint64_t mask = (unity << width) - 0x1;
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return ((word >> (width - 0x1)) & 0x1) ? (word | ~mask) : word;
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uint64_t mask = (unity << width) - 1;
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return ((word >> (width - 1)) & 0x1) ? (word | ~mask) : word;
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}
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inline __uint128_t sext128(__uint128_t word, uint32_t width) {
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@ -742,7 +742,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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uint32_t fflags = 0;
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switch (func7) {
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case 0x00: // RV32F: FADD.S
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rddata[t] = rv_fadd(rsdata[t][0], rsdata[t][1], frm, &fflags);
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rddata[t] = rv_fadd_s(rsdata[t][0], rsdata[t][1], frm, &fflags);
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trace->fpu.type = FpuType::FMA;
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trace->used_fregs.set(rsrc0);
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trace->used_fregs.set(rsrc1);
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@ -754,7 +754,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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trace->used_fregs.set(rsrc1);
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break;
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case 0x04: // RV32F: FSUB.S
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rddata[t] = rv_fsub(rsdata[t][0], rsdata[t][1], frm, &fflags);
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rddata[t] = rv_fsub_s(rsdata[t][0], rsdata[t][1], frm, &fflags);
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trace->fpu.type = FpuType::FMA;
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trace->used_fregs.set(rsrc0);
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trace->used_fregs.set(rsrc1);
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@ -766,7 +766,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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trace->used_fregs.set(rsrc1);
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break;
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case 0x08: // RV32F: FMUL.S
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rddata[t] = rv_fmul(rsdata[t][0], rsdata[t][1], frm, &fflags);
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rddata[t] = rv_fmul_s(rsdata[t][0], rsdata[t][1], frm, &fflags);
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trace->fpu.type = FpuType::FMA;
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trace->used_fregs.set(rsrc0);
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trace->used_fregs.set(rsrc1);
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@ -778,7 +778,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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trace->used_fregs.set(rsrc1);
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break;
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case 0x0c: // RV32F: FDIV.S
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rddata[t] = rv_fdiv(rsdata[t][0], rsdata[t][1], frm, &fflags);
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rddata[t] = rv_fdiv_s(rsdata[t][0], rsdata[t][1], frm, &fflags);
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trace->fpu.type = FpuType::FDIV;
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trace->used_fregs.set(rsrc0);
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trace->used_fregs.set(rsrc1);
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@ -790,7 +790,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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trace->used_fregs.set(rsrc1);
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break;
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case 0x2c: // RV32F: FSQRT.S
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rddata[t] = rv_fsqrt(rsdata[t][0], frm, &fflags);
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rddata[t] = rv_fsqrt_s(rsdata[t][0], frm, &fflags);
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trace->fpu.type = FpuType::FSQRT;
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trace->used_fregs.set(rsrc0);
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break;
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@ -802,13 +802,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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case 0x10:
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switch (func3) {
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case 0: // RV32F: FSGNJ.S
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rddata[t] = rv_fsgnj(rsdata[t][0], rsdata[t][1]);
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rddata[t] = rv_fsgnj_s(rsdata[t][0], rsdata[t][1]);
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break;
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case 1: // RV32F: FSGNJN.S
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rddata[t] = rv_fsgnjn(rsdata[t][0], rsdata[t][1]);
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rddata[t] = rv_fsgnjn_s(rsdata[t][0], rsdata[t][1]);
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break;
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case 2: // RV32F: FSGNJX.S
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rddata[t] = rv_fsgnjx(rsdata[t][0], rsdata[t][1]);
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rddata[t] = rv_fsgnjx_s(rsdata[t][0], rsdata[t][1]);
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break;
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}
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case 0x11:
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@ -830,10 +830,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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case 0x14:
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if (func3) {
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// RV32F: FMAX.S
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rddata[t] = rv_fmax(rsdata[t][0], rsdata[t][1], &fflags);
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rddata[t] = rv_fmax_s(rsdata[t][0], rsdata[t][1], &fflags);
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} else {
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// RV32F: FMIN.S
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rddata[t] = rv_fmin(rsdata[t][0], rsdata[t][1], &fflags);
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rddata[t] = rv_fmin_s(rsdata[t][0], rsdata[t][1], &fflags);
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}
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trace->fpu.type = FpuType::FNCP;
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trace->used_fregs.set(rsrc0);
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@ -855,19 +855,19 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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switch(rsrc1) {
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case 0:
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// RV32F: FCVT.W.S
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rddata[t] = sext64(rv_ftoi(rsdata[t][0], frm, &fflags), 32);
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rddata[t] = sext64(rv_ftoi_s(rsdata[t][0], frm, &fflags), 32);
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break;
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case 1:
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// RV32F: FCVT.WU.S
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rddata[t] = sext64(rv_ftou(rsdata[t][0], frm, &fflags), 32);
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rddata[t] = sext64(rv_ftou_s(rsdata[t][0], frm, &fflags), 32);
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break;
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case 2:
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// RV64F: FCVT.L.S
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rddata[t] = rv_ftol(rsdata[t][0], frm, &fflags);
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rddata[t] = rv_ftol_s(rsdata[t][0], frm, &fflags);
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break;
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case 3:
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// RV64F: FCVT.LU.S
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rddata[t] = rv_ftolu(rsdata[t][0], frm, &fflags);
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rddata[t] = rv_ftolu_s(rsdata[t][0], frm, &fflags);
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break;
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}
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trace->fpu.type = FpuType::FCVT;
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@ -898,7 +898,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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case 0x70:
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if (func3) {
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// RV32F: FCLASS.S
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rddata[t] = rv_fclss(rsdata[t][0]);
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rddata[t] = rv_fclss_s(rsdata[t][0]);
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} else {
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// RV32F: FMV.X.W
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rddata[t] = rsdata[t][0];
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@ -908,7 +908,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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break;
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case 0x71:
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if (func3) {
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// RV32D: FCLASS.S
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// RV32D: FCLASS.D
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rddata[t] = rv_fclss_d(rsdata[t][0]);
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} else {
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// RV64D: FMV.X.D
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@ -921,15 +921,15 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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switch(func3) {
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case 0:
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// RV32F: FLE.S
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rddata[t] = rv_fle(rsdata[t][0], rsdata[t][1], &fflags);
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rddata[t] = rv_fle_s(rsdata[t][0], rsdata[t][1], &fflags);
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break;
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case 1:
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// RV32F: FLT.S
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rddata[t] = rv_flt(rsdata[t][0], rsdata[t][1], &fflags);
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rddata[t] = rv_flt_s(rsdata[t][0], rsdata[t][1], &fflags);
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break;
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case 2:
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// RV32F: FEQ.S
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rddata[t] = rv_feq(rsdata[t][0], rsdata[t][1], &fflags);
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rddata[t] = rv_feq_s(rsdata[t][0], rsdata[t][1], &fflags);
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break;
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}
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trace->fpu.type = FpuType::FNCP;
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@ -959,19 +959,19 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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switch(rsrc1) {
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case 0:
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// RV32F: FCVT.S.W
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rddata[t] = rv_itof(rsdata[t][0], frm, &fflags);
|
||||
rddata[t] = rv_itof_s(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 1:
|
||||
// RV32F: FCVT.S.WU
|
||||
rddata[t] = rv_utof(rsdata[t][0], frm, &fflags);
|
||||
rddata[t] = rv_utof_s(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 2:
|
||||
// RV64F: FCVT.S.L
|
||||
rddata[t] = rv_ltof(rsdata[t][0], frm, &fflags);
|
||||
rddata[t] = rv_ltof_s(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 3:
|
||||
// RV64F: FCVT.S.LU
|
||||
rddata[t] = rv_lutof(rsdata[t][0], frm, &fflags);
|
||||
rddata[t] = rv_lutof_s(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FCVT;
|
||||
|
|
@ -1030,7 +1030,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
rddata[t] = rv_fmadd_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FMADD.S
|
||||
rddata[t] = rv_fmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
rddata[t] = rv_fmadd_s(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
case FMSUB:
|
||||
if (func2)
|
||||
|
|
@ -1038,7 +1038,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
rddata[t] = rv_fmsub_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FMSUB.S
|
||||
rddata[t] = rv_fmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
rddata[t] = rv_fmsub_s(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
case FMNMADD:
|
||||
if (func2)
|
||||
|
|
@ -1046,7 +1046,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
rddata[t] = rv_fnmadd_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FNMADD.S
|
||||
rddata[t] = rv_fnmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
rddata[t] = rv_fnmadd_s(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
case FMNMSUB:
|
||||
if (func2)
|
||||
|
|
@ -1054,7 +1054,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
rddata[t] = rv_fnmsub_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FNMSUB.S
|
||||
rddata[t] = rv_fnmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
rddata[t] = rv_fnmsub_s(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
ramulator.active_cycles_0 76 # Total active cycles for level _0
|
||||
ramulator.busy_cycles_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0
|
||||
ramulator.serving_requests_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0
|
||||
ramulator.average_serving_requests_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0
|
||||
ramulator.average_serving_requests_0 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0
|
||||
ramulator.active_cycles_0_0 76 # Total active cycles for level _0_0
|
||||
ramulator.busy_cycles_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0
|
||||
ramulator.serving_requests_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0
|
||||
ramulator.average_serving_requests_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0
|
||||
ramulator.average_serving_requests_0_0 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0
|
||||
ramulator.active_cycles_0_0_0 76 # Total active cycles for level _0_0_0
|
||||
ramulator.busy_cycles_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0
|
||||
ramulator.serving_requests_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0
|
||||
ramulator.average_serving_requests_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0
|
||||
ramulator.average_serving_requests_0_0_0 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0
|
||||
ramulator.active_cycles_0_0_0_0 76 # Total active cycles for level _0_0_0_0
|
||||
ramulator.busy_cycles_0_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0
|
||||
ramulator.serving_requests_0_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0
|
||||
ramulator.average_serving_requests_0_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0
|
||||
ramulator.average_serving_requests_0_0_0_0 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0
|
||||
ramulator.active_cycles_0_0_0_1 0 # Total active cycles for level _0_0_0_1
|
||||
ramulator.busy_cycles_0_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1
|
||||
ramulator.serving_requests_0_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1
|
||||
|
|
@ -106,9 +106,9 @@ ramulator.write_row_conflicts_channel_0_core 0
|
|||
ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR
|
||||
ramulator.read_latency_avg_0 26.333333 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel
|
||||
ramulator.read_latency_sum_0 79 # The memory latency cycles (in memory time domain) sum for all read requests in this channel
|
||||
ramulator.req_queue_length_avg_0 0.046529 # Average of read and write queue length per memory cycle per channel.
|
||||
ramulator.req_queue_length_avg_0 0.044681 # Average of read and write queue length per memory cycle per channel.
|
||||
ramulator.req_queue_length_sum_0 63 # Sum of read and write queue length per memory cycle per channel.
|
||||
ramulator.read_req_queue_length_avg_0 0.046529 # Read queue length average per memory cycle per channel.
|
||||
ramulator.read_req_queue_length_avg_0 0.044681 # Read queue length average per memory cycle per channel.
|
||||
ramulator.read_req_queue_length_sum_0 63 # Read queue length sum per memory cycle per channel.
|
||||
ramulator.write_req_queue_length_avg_0 0.000000 # Write queue length average per memory cycle per channel.
|
||||
ramulator.write_req_queue_length_sum_0 0 # Write queue length sum per memory cycle per channel.
|
||||
|
|
@ -127,19 +127,19 @@ ramulator.write_row_conflicts_channel_0_core 0
|
|||
ramulator.active_cycles_1 76 # Total active cycles for level _1
|
||||
ramulator.busy_cycles_1 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1
|
||||
ramulator.serving_requests_1 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1
|
||||
ramulator.average_serving_requests_1 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1
|
||||
ramulator.average_serving_requests_1 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1
|
||||
ramulator.active_cycles_1_0 76 # Total active cycles for level _1_0
|
||||
ramulator.busy_cycles_1_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0
|
||||
ramulator.serving_requests_1_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0
|
||||
ramulator.average_serving_requests_1_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0
|
||||
ramulator.average_serving_requests_1_0 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0
|
||||
ramulator.active_cycles_1_0_0 76 # Total active cycles for level _1_0_0
|
||||
ramulator.busy_cycles_1_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0
|
||||
ramulator.serving_requests_1_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0
|
||||
ramulator.average_serving_requests_1_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0
|
||||
ramulator.average_serving_requests_1_0_0 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0
|
||||
ramulator.active_cycles_1_0_0_0 76 # Total active cycles for level _1_0_0_0
|
||||
ramulator.busy_cycles_1_0_0_0 76 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_0
|
||||
ramulator.serving_requests_1_0_0_0 76 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0
|
||||
ramulator.average_serving_requests_1_0_0_0 0.056130 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0
|
||||
ramulator.average_serving_requests_1_0_0_0 0.053901 # The average of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_0
|
||||
ramulator.active_cycles_1_0_0_1 0 # Total active cycles for level _1_0_0_1
|
||||
ramulator.busy_cycles_1_0_0_1 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _1_0_0_1
|
||||
ramulator.serving_requests_1_0_0_1 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _1_0_0_1
|
||||
|
|
@ -232,9 +232,9 @@ ramulator.write_row_conflicts_channel_1_core 0
|
|||
ramulator.useless_activates_1_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR
|
||||
ramulator.read_latency_avg_1 26.333333 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel
|
||||
ramulator.read_latency_sum_1 79 # The memory latency cycles (in memory time domain) sum for all read requests in this channel
|
||||
ramulator.req_queue_length_avg_1 0.046529 # Average of read and write queue length per memory cycle per channel.
|
||||
ramulator.req_queue_length_avg_1 0.044681 # Average of read and write queue length per memory cycle per channel.
|
||||
ramulator.req_queue_length_sum_1 63 # Sum of read and write queue length per memory cycle per channel.
|
||||
ramulator.read_req_queue_length_avg_1 0.046529 # Read queue length average per memory cycle per channel.
|
||||
ramulator.read_req_queue_length_avg_1 0.044681 # Read queue length average per memory cycle per channel.
|
||||
ramulator.read_req_queue_length_sum_1 63 # Read queue length sum per memory cycle per channel.
|
||||
ramulator.write_req_queue_length_avg_1 0.000000 # Write queue length average per memory cycle per channel.
|
||||
ramulator.write_req_queue_length_sum_1 0 # Write queue length sum per memory cycle per channel.
|
||||
|
|
@ -251,7 +251,7 @@ ramulator.write_row_conflicts_channel_1_core 0
|
|||
ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end
|
||||
[0] 0.0 #
|
||||
ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM
|
||||
ramulator.dram_cycles 1354 # Number of DRAM cycles simulated
|
||||
ramulator.dram_cycles 1410 # Number of DRAM cycles simulated
|
||||
ramulator.incoming_requests 6 # Number of incoming requests to DRAM
|
||||
ramulator.read_requests 6 # Number of incoming read requests to DRAM per core
|
||||
[0] 6.0 #
|
||||
|
|
@ -269,8 +269,8 @@ ramulator.incoming_read_reqs_per_channel 6.0
|
|||
ramulator.in_queue_req_num_sum 126 # Sum of read/write queue length
|
||||
ramulator.in_queue_read_req_num_sum 126 # Sum of read queue length
|
||||
ramulator.in_queue_write_req_num_sum 0 # Sum of write queue length
|
||||
ramulator.in_queue_req_num_avg 0.093058 # Average of read/write queue length per memory cycle
|
||||
ramulator.in_queue_read_req_num_avg 0.093058 # Average of read queue length per memory cycle
|
||||
ramulator.in_queue_req_num_avg 0.089362 # Average of read/write queue length per memory cycle
|
||||
ramulator.in_queue_read_req_num_avg 0.089362 # Average of read queue length per memory cycle
|
||||
ramulator.in_queue_write_req_num_avg 0.000000 # Average of write queue length per memory cycle
|
||||
ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end
|
||||
[0] 0.0 #
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue