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+Added icache stage -- 3rd case of AUIPC os broken?

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felsabbagh3 2020-03-01 18:01:02 -08:00
parent ca61801199
commit f98f5c414d
4 changed files with 96 additions and 37 deletions
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48
rtl/VX_fetch.v
View file

@ -7,26 +7,39 @@ module VX_fetch (
VX_wstall_inter VX_wstall,
VX_join_inter VX_join,
input wire schedule_delay,
VX_icache_response_inter icache_response,
VX_icache_request_inter icache_request,
input wire icache_stage_delay,
output wire out_ebreak,
VX_jal_response_inter VX_jal_rsp,
VX_branch_response_inter VX_branch_rsp,
VX_inst_meta_inter fe_inst_meta_fd,
VX_inst_meta_inter fe_inst_meta_fi,
VX_warp_ctl_inter VX_warp_ctl
);
// Locals
wire pipe_stall;
assign pipe_stall = schedule_delay || icache_response.delay;
wire[`NT_M1:0] thread_mask;
wire[`NW_M1:0] warp_num;
wire[31:0] warp_pc;
wire scheduled_warp;
// Only reason this is there is because there is a hidden assumption that decode is exactly after fetch
reg stall_might_be_branch;
always @(posedge clk) begin
if (reset) begin
stall_might_be_branch <= 0;
end else if (stall_might_be_branch == 1'b1) begin
stall_might_be_branch <= 0;
end else if (scheduled_warp == 1'b1) begin
stall_might_be_branch <= 1'b1;
end
end
// Locals
wire pipe_stall;
assign pipe_stall = schedule_delay || icache_stage_delay || stall_might_be_branch;
VX_warp_scheduler warp_scheduler(
.clk (clk),
.reset (reset),
@ -82,22 +95,11 @@ module VX_fetch (
.out_ebreak (out_ebreak),
.scheduled_warp (scheduled_warp)
);
// always @(*) begin
// $display("Inside verilog instr: %h, pc: %h", icache_response.instruction, warp_pc);
// end
assign icache_request.pc_address = warp_pc;
assign icache_request.out_cache_driver_in_valid = !schedule_delay && scheduled_warp;
assign icache_request.out_cache_driver_in_mem_read = `LW_MEM_READ;
assign icache_request.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
assign icache_request.out_cache_driver_in_data = 32'b0;
assign fe_inst_meta_fi.warp_num = warp_num;
assign fe_inst_meta_fi.valid = thread_mask;
assign fe_inst_meta_fd.warp_num = warp_num;
assign fe_inst_meta_fd.valid = thread_mask;
assign fe_inst_meta_fd.instruction = (thread_mask == 0) ? 32'b0 : icache_response.instruction;
assign fe_inst_meta_fd.inst_pc = warp_pc;
assign fe_inst_meta_fi.inst_pc = warp_pc;
endmodule

35
rtl/VX_front_end.v
View file

@ -20,12 +20,15 @@ module VX_front_end (
);
VX_inst_meta_inter fe_inst_meta_fd();
VX_inst_meta_inter fe_inst_meta_fi();
VX_inst_meta_inter fe_inst_meta_fi2();
VX_inst_meta_inter fe_inst_meta_id();
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req();
VX_inst_meta_inter fd_inst_meta_de();
wire total_freeze = schedule_delay;
wire icache_stage_delay;
/* verilator lint_off UNUSED */
// wire real_fetch_ebreak;
@ -47,20 +50,38 @@ VX_fetch vx_fetch(
.VX_join (VX_join),
.schedule_delay (schedule_delay),
.VX_jal_rsp (VX_jal_rsp),
.icache_response (icache_response_fe),
.VX_warp_ctl (VX_warp_ctl),
.icache_request (icache_request_fe),
.icache_stage_delay (icache_stage_delay),
.VX_branch_rsp (VX_branch_rsp),
.out_ebreak (vortex_ebreak), // fetch_ebreak
.fe_inst_meta_fd (fe_inst_meta_fd)
.fe_inst_meta_fi (fe_inst_meta_fi)
);
VX_f_d_reg vx_f_d_reg(
wire freeze_fi_reg = total_freeze || icache_stage_delay;
VX_f_d_reg vx_f_i_reg(
.clk (clk),
.reset (reset),
.in_freeze (freeze_fi_reg),
.fe_inst_meta_fd(fe_inst_meta_fi),
.fd_inst_meta_de(fe_inst_meta_fi2)
);
VX_icache_stage VX_icache_stage(
.clk (clk),
.reset (reset),
.icache_stage_delay(icache_stage_delay),
.fe_inst_meta_fi (fe_inst_meta_fi2),
.fe_inst_meta_id (fe_inst_meta_id),
.icache_response (icache_response_fe),
.icache_request (icache_request_fe)
);
VX_f_d_reg vx_i_d_reg(
.clk (clk),
.reset (reset),
.in_freeze (total_freeze),
.fe_inst_meta_fd(fe_inst_meta_fd),
.fe_inst_meta_fd(fe_inst_meta_id),
.fd_inst_meta_de(fd_inst_meta_de)
);

31
rtl/VX_icache_stage.v Normal file
View file

@ -0,0 +1,31 @@
`include "VX_define.v"
module VX_icache_stage (
input wire clk,
input wire reset,
output wire icache_stage_delay,
VX_inst_meta_inter fe_inst_meta_fi,
VX_inst_meta_inter fe_inst_meta_id,
VX_icache_response_inter icache_response,
VX_icache_request_inter icache_request
);
wire valid_inst = (|fe_inst_meta_fi.valid);
assign icache_request.pc_address = fe_inst_meta_fi.inst_pc;
assign icache_request.out_cache_driver_in_valid = fe_inst_meta_fi.valid != 0;
assign icache_request.out_cache_driver_in_mem_read = `LW_MEM_READ;
assign icache_request.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
assign icache_request.out_cache_driver_in_data = 32'b0;
assign icache_stage_delay = icache_response.delay;
assign fe_inst_meta_id.instruction = (!valid_inst || icache_response.delay) ? 32'b0 : icache_response.instruction;
assign fe_inst_meta_id.inst_pc = fe_inst_meta_fi.inst_pc;
assign fe_inst_meta_id.warp_num = fe_inst_meta_fi.warp_num;
assign fe_inst_meta_id.valid = fe_inst_meta_fi.valid;
endmodule

19
rtl/simulate/test_bench.cpp
View file

@ -67,14 +67,19 @@ int main(int argc, char **argv)
for (std::string s : tests) {
Vortex v;
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << s << std::endl;
bool curr = v.simulate(s);
if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
std::cerr << DEFAULT;
passed = passed && curr;
}
std::cerr << DEFAULT << "\n***************************************\n";
if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
@ -82,15 +87,15 @@ int main(int argc, char **argv)
#else
char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
char testing[] = "../../emulator/riscv_tests/rv32ui-p-auipc.hex";
Vortex v;
const char *testing;
// const char *testing;
if (argc >= 2) {
testing = argv[1];
} else {
testing = "../../kernel/vortex_test.hex";
}
// if (argc >= 2) {
// testing = argv[1];
// } else {
// testing = "../../kernel/vortex_test.hex";
// }
std::cerr << testing << std::endl;