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minor updates

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This commit is contained in:
Blaise Tine 2024-08-28 21:31:09 -07:00
parent a38960674e
commit fa1fd39645
23 changed files with 37 additions and 39 deletions
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2
hw/rtl/cache/VX_cache.sv vendored
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@ -136,7 +136,7 @@ module VX_cache import VX_gpu_pkg::*; #(
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s;
wire [NUM_REQS-1:0] core_rsp_ready_s;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : core_rsp_bufs
VX_elastic_buffer #(
.DATAW (`CS_WORD_WIDTH + TAG_WIDTH),
.SIZE (CORE_RSP_REG_DISABLE ? `TO_OUT_BUF_SIZE(CORE_OUT_BUF) : 0),

2
hw/rtl/cache/VX_cache_cluster.sv vendored
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@ -102,7 +102,7 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.TAG_WIDTH (ARB_TAG_WIDTH)
) arb_core_bus_if[NUM_CACHES * NUM_REQS]();
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar i = 0; i < NUM_REQS; ++i) begin : core_arbs
VX_mem_bus_if #(
.DATA_SIZE (WORD_SIZE),
.TAG_WIDTH (TAG_WIDTH)

2
hw/rtl/cache/VX_cache_tags.sv vendored
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@ -100,7 +100,7 @@ module VX_cache_tags #(
wire fill_s = fill && (!WRITEBACK || ~stall);
wire flush_s = flush && (!WRITEBACK || ~stall);
for (genvar i = 0; i < NUM_WAYS; ++i) begin : ways
for (genvar i = 0; i < NUM_WAYS; ++i) begin : tag_stores
wire do_fill = fill_s && evict_way[i];
wire do_flush = flush_s && (!WRITEBACK || way_sel[i]); // flush the whole line in writethrough mode

2
hw/rtl/core/VX_alu_unit.sv
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@ -55,7 +55,7 @@ module VX_alu_unit #(
.NUM_LANES (NUM_LANES)
) per_block_commit_if[BLOCK_SIZE]();
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : alu_blocks
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : alus
`RESET_RELAY_EN (block_reset, reset, (BLOCK_SIZE > 1));

2
hw/rtl/core/VX_commit.sv
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@ -41,7 +41,7 @@ module VX_commit import VX_gpu_pkg::*; #(
wire [`ISSUE_WIDTH-1:0][`NUM_THREADS-1:0] per_issue_commit_tmask;
wire [`ISSUE_WIDTH-1:0] per_issue_commit_eop;
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : commit_arbs
wire [`NUM_EX_UNITS-1:0] valid_in;
wire [`NUM_EX_UNITS-1:0][DATAW-1:0] data_in;

2
hw/rtl/core/VX_dispatch.sv
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@ -53,7 +53,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
wire [`NUM_EX_UNITS-1:0] operands_ready_in;
assign operands_if.ready = operands_ready_in[operands_if.data.ex_type];
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin
for (genvar i = 0; i < `NUM_EX_UNITS; ++i) begin : buffers
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (2),

2
hw/rtl/core/VX_fetch.sv
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@ -71,7 +71,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
// This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache requests.
// This issue is particularly prevalent when the icache and dcache are disabled and both requests share the same bus.
wire [`NUM_WARPS-1:0] pending_ibuf_full;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : pending_reads
VX_pending_size #(
.SIZE (`IBUF_SIZE)
) pending_reads (

2
hw/rtl/core/VX_fpu_unit.sv
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@ -53,7 +53,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
.NUM_LANES (NUM_LANES)
) per_block_commit_if[BLOCK_SIZE]();
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : fpu_blocks
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : fpus
`UNUSED_VAR (per_block_execute_if[block_idx].data.tid)
`UNUSED_VAR (per_block_execute_if[block_idx].data.wb)

2
hw/rtl/core/VX_gather_unit.sv
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@ -74,7 +74,7 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
assign commit_in_ready[i] = commit_out_ready[commit_in_isw[i]];
end
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin: out_bufs
VX_commit_if #(
.NUM_LANES (NUM_LANES)
) commit_tmp_if();

2
hw/rtl/core/VX_ibuffer.sv
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@ -35,7 +35,7 @@ module VX_ibuffer import VX_gpu_pkg::*; #(
wire [PER_ISSUE_WARPS-1:0] ibuf_ready_in;
assign decode_if.ready = ibuf_ready_in[decode_if.data.wid];
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : ibuf_slices
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : instr_bufs
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`IBUF_SIZE),

2
hw/rtl/core/VX_lsu_unit.sv
View file

@ -54,7 +54,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
.NUM_LANES (NUM_LANES)
) per_block_commit_if[BLOCK_SIZE]();
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : lsu_blocks
for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : lsus
`RESET_RELAY_EN (slice_reset, reset, (BLOCK_SIZE > 1));

8
hw/rtl/core/VX_mem_unit.sv
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@ -45,7 +45,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (LSU_TAG_WIDTH)
) lsu_lmem_if[`NUM_LSU_BLOCKS]();
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : demux_slices
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_switches
VX_lmem_switch #(
.REQ0_OUT_BUF (3),
.REQ1_OUT_BUF (0),
@ -65,7 +65,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (LSU_TAG_WIDTH)
) lmem_bus_if[LSU_NUM_REQS]();
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_adapter_slices
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : lmem_adapters
VX_mem_bus_if #(
.DATA_SIZE (LSU_WORD_SIZE),
.TAG_WIDTH (LSU_TAG_WIDTH)
@ -131,7 +131,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
if (LSU_WORD_SIZE != DCACHE_WORD_SIZE) begin : coalescer_if
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : coalescer_blocks
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : coalescers
`RESET_RELAY (mem_coalescer_reset, reset);
@ -195,7 +195,7 @@ module VX_mem_unit import VX_gpu_pkg::*; #(
end
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : dcache_adapter_slices
for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : dcache_adapters
VX_mem_bus_if #(
.DATA_SIZE (DCACHE_WORD_SIZE),

2
hw/rtl/core/VX_operands.sv
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@ -246,7 +246,7 @@ module VX_operands import VX_gpu_pkg::*; #(
assign gpr_wr_bank_idx = '0;
end
for (genvar b = 0; b < NUM_BANKS; ++b) begin
for (genvar b = 0; b < NUM_BANKS; ++b) begin : gpr_rams
wire gpr_wr_enabled;
if (BANK_SEL_BITS != 0) begin
assign gpr_wr_enabled = writeback_if.valid

2
hw/rtl/core/VX_schedule.sv
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@ -379,7 +379,7 @@ module VX_schedule import VX_gpu_pkg::*; #(
`RESET_RELAY (pending_instr_reset, reset);
for (genvar i = 0; i < `NUM_WARPS; ++i) begin
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : pending_sizes
VX_pending_size #(
.SIZE (4096),
.ALM_EMPTY (1)

2
hw/rtl/core/VX_scoreboard.sv
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@ -101,7 +101,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
end
`endif
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin
for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : stanging_bufs
VX_pipe_buffer #(
.DATAW (DATAW)
) stanging_buf (

2
hw/rtl/core/VX_split_join.sv
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@ -45,7 +45,7 @@ module VX_split_join import VX_gpu_pkg::*; #(
wire ipdom_push = valid && split.valid && split.is_dvg;
wire ipdom_pop = valid && sjoin.valid && sjoin_is_dvg;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : ipdom_slices
for (genvar i = 0; i < `NUM_WARPS; ++i) begin : ipdom_stacks
VX_ipdom_stack #(
.WIDTH (`NUM_THREADS+`PC_BITS),
.DEPTH (`DV_STACK_SIZE)

2
hw/rtl/fpu/VX_fpu_cvt.sv
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@ -86,7 +86,7 @@ module VX_fpu_cvt import VX_fpu_pkg::*; #(
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
end
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fcvt_units
VX_fcvt_unit #(
.LATENCY (`LATENCY_FCVT),
.OUT_REG (1)

6
hw/rtl/fpu/VX_fpu_div.sv
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@ -94,7 +94,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
`ifdef QUARTUS
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fdivs
acl_fdiv fdiv (
.clk (clk),
.areset (1'b0),
@ -112,7 +112,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
`elsif VIVADO
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fdivs
wire [3:0] tuser;
xil_fdiv fdiv (
.aclk (clk),
@ -134,7 +134,7 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
`else
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin fdivs
reg [63:0] r;
`UNUSED_VAR (r)
fflags_t f;

6
hw/rtl/fpu/VX_fpu_fma.sv
View file

@ -125,7 +125,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
`ifdef QUARTUS
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fmadds
acl_fmadd fmadd (
.clk (clk),
.areset (1'b0),
@ -143,7 +143,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
`elsif VIVADO
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fmas
wire [2:0] tuser;
xil_fma fma (
@ -168,7 +168,7 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
`else
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fmas
reg [63:0] r;
`UNUSED_VAR (r)
fflags_t f;

2
hw/rtl/fpu/VX_fpu_fpnew.sv
View file

@ -162,7 +162,7 @@ module VX_fpu_fpnew
end
`UNUSED_VAR (mask_in)
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar i = 0; i < NUM_LANES; ++i) begin : fpnew_cores
wire [(TAG_WIDTH+1)-1:0] fpu_tag;
wire fpu_valid_out_uq;
wire fpu_ready_in_uq;

2
hw/rtl/fpu/VX_fpu_ncp.sv
View file

@ -91,7 +91,7 @@ module VX_fpu_ncp import VX_fpu_pkg::*; #(
assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS];
end
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fncp_units
VX_fncp_unit #(
.LATENCY (`LATENCY_FNCP),
.OUT_REG (1)

6
hw/rtl/fpu/VX_fpu_sqrt.sv
View file

@ -88,7 +88,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
`ifdef QUARTUS
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
acl_fsqrt fsqrt (
.clk (clk),
.areset (1'b0),
@ -105,7 +105,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
`elsif VIVADO
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
wire tuser;
xil_fsqrt fsqrt (
@ -126,7 +126,7 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
`else
for (genvar i = 0; i < NUM_PES; ++i) begin
for (genvar i = 0; i < NUM_PES; ++i) begin : fsqrts
reg [63:0] r;
`UNUSED_VAR (r)
fflags_t f;

14
hw/rtl/libs/VX_avs_adapter.sv
View file

@ -64,7 +64,6 @@ module VX_avs_adapter #(
wire [NUM_BANKS-1:0] req_queue_push, req_queue_pop;
wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] req_queue_tag_out;
wire [NUM_BANKS-1:0] req_queue_going_full;
wire [NUM_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size;
wire [BANK_ADDRW-1:0] req_bank_sel;
wire [BANK_OFFSETW-1:0] req_bank_off;
wire [NUM_BANKS-1:0] bank_req_ready;
@ -81,8 +80,7 @@ module VX_avs_adapter #(
assign req_queue_push[i] = mem_req_valid && ~mem_req_rw && bank_req_ready[i] && (req_bank_sel == i);
end
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : pending_sizes
VX_pending_size #(
.SIZE (RD_QUEUE_SIZE)
) pending_size (
@ -94,10 +92,11 @@ module VX_avs_adapter #(
`UNUSED_PIN (alm_empty),
.full (req_queue_going_full[i]),
`UNUSED_PIN (alm_full),
.size (req_queue_size[i])
`UNUSED_PIN (size)
);
`UNUSED_VAR (req_queue_size)
end
for (genvar i = 0; i < NUM_BANKS; ++i) begin : rd_req_queues
VX_fifo_queue #(
.DATAW (TAG_WIDTH),
.DEPTH (RD_QUEUE_SIZE)
@ -116,7 +115,7 @@ module VX_avs_adapter #(
);
end
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : req_out_bufs
wire valid_out;
wire rw_out;
wire [DATA_SIZE-1:0] byteen_out;
@ -168,8 +167,7 @@ module VX_avs_adapter #(
wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] rsp_queue_data_out;
wire [NUM_BANKS-1:0] rsp_queue_empty;
for (genvar i = 0; i < NUM_BANKS; ++i) begin
for (genvar i = 0; i < NUM_BANKS; ++i) begin : rd_rsp_queues
VX_fifo_queue #(
.DATAW (DATA_WIDTH),
.DEPTH (RD_QUEUE_SIZE)