mirror of
https://github.com/vortexgpgpu/vortex.git
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bilinear fixes + refactoring
This commit is contained in:
Blaise Tine
parent
99ca04ce8c
commit
fa2d84831e
7 changed files with 106 additions and 223 deletions
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@ -1,68 +0,0 @@
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`include "VX_tex_define.vh"
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module VX_tex_bilerp #(
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parameter CORE_ID = 0
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) (
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input wire [`BLEND_FRAC_64-1:0] blendU,
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input wire [`BLEND_FRAC_64-1:0] blendV,
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input wire [3:0][63:0] texels,
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input wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
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output wire [31:0] sampled_data
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);
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`UNUSED_PARAM (CORE_ID)
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wire [63:0] UL_lerp;
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wire [63:0] UH_lerp;
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wire [63:0] V_lerp;
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reg [31:0] sampled_r;
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VX_tex_lerp #(
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) tex_lerp_UL (
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.blend(blendU),
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.in_texels({texels[1], texels[0]}),
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.lerp_texel(UL_lerp)
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);
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VX_tex_lerp #(
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) tex_lerp_UH (
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.blend(blendU),
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.in_texels({texels[3], texels[2]}),
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.lerp_texel(UH_lerp)
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);
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VX_tex_lerp #(
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) tex_lerp_V (
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.blend(blendV),
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.in_texels({UH_lerp, UL_lerp}),
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.lerp_texel(V_lerp)
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);
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`UNUSED_VAR (V_lerp[63:56])
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always @(*) begin
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if (color_enable[3]==1'b1) //R
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sampled_r[31:24] = V_lerp[55:48];
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else
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sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}};
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if (color_enable[2]==1'b1) //G
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sampled_r[23:16] = V_lerp[39:32];
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else
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sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}};
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if (color_enable[1]==1'b1) //B
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sampled_r[15:8] = V_lerp[23:16];
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else
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sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}};
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if (color_enable[0]==1'b1) //A
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sampled_r[7:0] = V_lerp[7:0];
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else
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sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}};
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end
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assign sampled_data = sampled_r;
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endmodule
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@ -11,10 +11,6 @@
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`define CLAMP(x,lo,hi) (($signed(x) < $signed(lo)) ? lo : ((x > hi) ? hi : x))
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`define BLEND_FRAC_64 8
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`define LERP_64(x1,x2,frac) ((x2 + (((x1 - x2) * frac) >> `BLEND_FRAC_64)) & 64'h00ff00ff00ff00ff)
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`define TEX_ADDR_BITS 32
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`define TEX_FORMAT_BITS 3
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`define TEX_WRAP_BITS 2
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@ -32,10 +28,8 @@
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`define TEX_WRAP_REPEAT 1
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`define TEX_WRAP_MIRROR 2
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`define MAX_COLOR_WIDTH 8
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`define NUM_COLOR_CHANNEL 4
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`define TEX_COLOR_BITS 8
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`define BLEND_FRAC 8
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`define TEX_FORMAT_R8G8B8A8 `TEX_FORMAT_BITS'(0)
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`define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1)
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@ -1,125 +1,57 @@
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`include "VX_tex_define.vh"
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module VX_tex_format #(
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parameter CORE_ID = 0,
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parameter NUM_TEXELS = 4 //BILINEAR
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parameter CORE_ID = 0
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) (
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input wire [NUM_TEXELS-1:0][31:0] texel_data,
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input wire [`TEX_FORMAT_BITS-1:0] format,
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output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
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output wire [NUM_TEXELS-1:0][63:0] formatted_lerp_texel,
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output wire [31:0] formatted_pt_texel
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input wire [`TEX_FORMAT_BITS-1:0] format,
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input wire [31:0] texel_in,
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output wire [31:0] texel_out
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
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reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
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reg [31:0] formatted_pt_r;
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reg [31:0] texel_out_r;
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always @(*) begin
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// bilerp/trilerp input
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for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
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case (format)
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`TEX_FORMAT_R5G6B5: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][4:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][10:5]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][15:11]);
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formatted_texel_r[i][55:48] = {`TEX_COLOR_BITS{1'b0}};
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if (i == 0)
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color_enable_r = 4'b0111;
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end
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`TEX_FORMAT_R4G4B4A4: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][3:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][7:4]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][11:8]);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:12]);
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if (i == 0)
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color_enable_r = 4'b1111;
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end
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`TEX_FORMAT_L8A8: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
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if (i == 0)
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color_enable_r = 4'b0011;
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end
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`TEX_FORMAT_A8: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
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if (i == 0)
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color_enable_r = 4'b0001;
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end
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`TEX_FORMAT_L8: begin
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
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if (i == 0)
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color_enable_r = 4'b0001;
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end
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default: begin // `TEX_FORMAT_R8G8B8A8:
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formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
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formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
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formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
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formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][31:24]);
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if (i == 0)
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color_enable_r = 4'b1111;
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end
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endcase
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end
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// pt sampling direct output
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always @(*) begin
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case (format)
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`TEX_FORMAT_R5G6B5: begin
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formatted_pt_r[07:00] = {`TEX_COLOR_BITS{1'b1}};
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][4:0]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][10:5]);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][15:11]);
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end
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`TEX_FORMAT_R4G4B4A4: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][3:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][7:4]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][11:8]);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][15:12]);
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end
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`TEX_FORMAT_L8A8: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][15:8]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
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end
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`TEX_FORMAT_A8: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
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end
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`TEX_FORMAT_L8: begin
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
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end
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default: begin // `TEX_FORMAT_R8G8B8A8:
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formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
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formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][15:8]);
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formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][23:16]);
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formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][31:24]);
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end
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`TEX_FORMAT_R5G6B5: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[4:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[10:5]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[15:11]);
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texel_out_r[31:24] = {`TEX_COLOR_BITS{1'b1}};
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end
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`TEX_FORMAT_R4G4B4A4: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[3:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[7:4]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[11:8]);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[15:12]);
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end
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`TEX_FORMAT_L8A8: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[15:8]);
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end
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`TEX_FORMAT_A8: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(0);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(0);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(0);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[7:0]);
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end
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`TEX_FORMAT_L8: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[31:24] = {`TEX_COLOR_BITS{1'b1}};
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end
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default: begin // `TEX_FORMAT_R8G8B8A8:
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[15:8]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[23:16]);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[31:24]);
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end
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endcase
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end
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assign color_enable = color_enable_r;
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assign formatted_pt_texel = formatted_pt_r;
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for (genvar i = 0; i < NUM_TEXELS; i++) begin
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assign formatted_lerp_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
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end
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assign texel_out = texel_out_r;
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endmodule
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@ -2,19 +2,34 @@
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module VX_tex_lerp #(
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) (
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input wire [`BLEND_FRAC_64-1:0] blend,
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input wire [1:0][63:0] in_texels,
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output wire [63:0] lerp_texel
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input wire [`BLEND_FRAC-1:0] blend,
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input wire [31:0] in1,
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input wire [31:0] in2,
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output wire [31:0] out
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);
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wire [63:0] in1_w, in2_w;
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wire [63:0] lerp1, lerp2;
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`UNUSED_VAR (lerp_i1[55:48])
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`UNUSED_VAR (lerp1)
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`UNUSED_VAR (lerp2)
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wire [63:0] lerp_i1;
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wire [63:0] lerp_i2; // >> BLEND_FRAC_64 / >> 8
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assign in1_w[15:00] = {8'h00, in1[07:00]};
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assign in1_w[31:16] = {8'h00, in1[15:08]};
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assign in1_w[47:32] = {8'h00, in1[23:16]};
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assign in1_w[63:48] = {8'h00, in1[31:24]};
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assign lerp_i1 = (in_texels[0] - in_texels[1]) * blend;
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assign lerp_i2 = in_texels[1] + {8'h00,lerp_i1[63:56], 8'h00,lerp_i1[47:40], 8'h00,lerp_i1[31:24], 8'h00,lerp_i1[15:8]};
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assign lerp_texel = lerp_i2 & 64'h00ff00ff00ff00ff;
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assign in2_w[15:00] = {8'h00, in2[07:00]};
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assign in2_w[31:16] = {8'h00, in2[15:08]};
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assign in2_w[47:32] = {8'h00, in2[23:16]};
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assign in2_w[63:48] = {8'h00, in2[31:24]};
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assign lerp1 = (in2_w - in1_w) * blend;
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assign lerp2 = in1_w + {8'h00,lerp1[63:56], 8'h00,lerp1[47:40], 8'h00,lerp1[31:24], 8'h00,lerp1[15:8]};
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assign out[07:00] = lerp2[07:00];
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assign out[15:08] = lerp2[23:16];
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assign out[23:16] = lerp2[39:32];
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assign out[31:24] = lerp2[55:48];
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endmodule
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@ -278,7 +278,7 @@ module VX_tex_memory #(
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_filter);
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`PRINT_ARRAY2D(rsp_data, 4, `NUM_THREADS);
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$write("\n");
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end
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end
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end
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`endif
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@ -39,37 +39,47 @@ module VX_tex_sampler #(
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] req_data_bilerp;
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wire [3:0][63:0] formatted_data;
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wire [31:0] formatted_pt_data;
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wire [`NUM_COLOR_CHANNEL-1:0] color_enable;
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wire [3:0][31:0] fmt_texels;
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wire [31:0] texel_ul, texel_uh, texel_v;
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VX_tex_format #(
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.CORE_ID (CORE_ID),
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.NUM_TEXELS (4)
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) tex_format (
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.texel_data (req_texels[i]),
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.format (req_format),
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wire [`BLEND_FRAC-1:0] blend_u = req_u[i][`BLEND_FRAC-1:0];
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wire [`BLEND_FRAC-1:0] blend_v = req_v[i][`BLEND_FRAC-1:0];
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.color_enable (color_enable),
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.formatted_lerp_texel(formatted_data),
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.formatted_pt_texel(formatted_pt_data)
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for (genvar j = 0; j < 4; j++) begin
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VX_tex_format #(
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.CORE_ID (CORE_ID)
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) tex_format (
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.format (req_format),
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.texel_in (req_texels[i][j]),
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.texel_out (fmt_texels[j])
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);
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end
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VX_tex_lerp #(
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) tex_lerp_ul (
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.blend (blend_u),
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.in1 (fmt_texels[0]),
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.in2 (fmt_texels[1]),
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.out (texel_ul)
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);
|
||||
|
||||
VX_tex_bilerp #(
|
||||
.CORE_ID (CORE_ID)
|
||||
) tex_bilerp (
|
||||
.blendU (req_u[i][`BLEND_FRAC_64-1:0]),
|
||||
.blendV (req_v[i][`BLEND_FRAC_64-1:0]),
|
||||
VX_tex_lerp #(
|
||||
) tex_lerp_uh (
|
||||
.blend (blend_u),
|
||||
.in1 (fmt_texels[2]),
|
||||
.in2 (fmt_texels[3]),
|
||||
.out (texel_uh)
|
||||
);
|
||||
|
||||
.color_enable (color_enable),
|
||||
.texels (formatted_data),
|
||||
|
||||
.sampled_data (req_data_bilerp)
|
||||
);
|
||||
|
||||
assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? formatted_pt_data : req_data_bilerp;
|
||||
VX_tex_lerp #(
|
||||
) tex_lerp_v (
|
||||
.blend (blend_v),
|
||||
.in1 (texel_ul),
|
||||
.in2 (texel_uh),
|
||||
.out (texel_v)
|
||||
);
|
||||
|
||||
assign req_data[i] = req_filter ? texel_v : fmt_texels[0];
|
||||
end
|
||||
|
||||
assign stall_out = rsp_valid && ~rsp_ready;
|
||||
|
|
|
|||
|
|
@ -190,7 +190,7 @@ module VX_tex_unit #(
|
|||
wire [`NR_BITS-1:0] rsp_rd;
|
||||
wire rsp_wb;
|
||||
|
||||
assign {rsp_format, rsp_u, rsp_v, rsp_rd, rsp_wb} = mem_rsp_info;
|
||||
assign {rsp_u, rsp_v, rsp_format, rsp_rd, rsp_wb} = mem_rsp_info;
|
||||
|
||||
VX_tex_sampler #(
|
||||
.CORE_ID (CORE_ID)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue