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Finalized GPR with 3-Port Structure

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This commit is contained in:
felsabbagh3 2019-09-11 14:53:32 -04:00
parent 1b25b10644
commit fb3bc60189
13 changed files with 1440 additions and 4192 deletions
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60
rtl/VX_gpr.v
View file

@ -14,32 +14,50 @@ module VX_gpr (
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
// USING RAM blocks
// First RAM
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr(VX_writeback_inter.rd),
.raddr(VX_gpr_read.rs1),
.be (VX_writeback_inter.wb_valid),
.wdata(VX_writeback_inter.write_data),
.q (out_a_reg_data)
);
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
// Second RAM block
byte_enabled_simple_dual_port_ram second_ram(
.we (write_enable),
.clk (clk),
.waddr(VX_writeback_inter.rd),
.raddr(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata(VX_writeback_inter.write_data),
.q (out_b_reg_data)
);
// // USING RAM blocks
// // First RAM
// byte_enabled_simple_dual_port_ram first_ram(
// .we (write_enable),
// .clk (clk),
// .waddr(VX_writeback_inter.rd),
// .raddr(VX_gpr_read.rs1),
// .be (VX_writeback_inter.wb_valid),
// .wdata(VX_writeback_inter.write_data),
// .q (out_a_reg_data)
// );
// // Second RAM block
// byte_enabled_simple_dual_port_ram second_ram(
// .we (write_enable),
// .clk (clk),
// .waddr(VX_writeback_inter.rd),
// .raddr(VX_gpr_read.rs2),
// .be (VX_writeback_inter.wb_valid),
// .wdata(VX_writeback_inter.write_data),
// .q (out_b_reg_data)
// );
// logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
// wire write_enable;

37
rtl/VX_gpr_syn.v
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@ -21,27 +21,40 @@ module VX_gpr_syn (
input wire[`NW_M1:0] wb_warp_num,
/////////
output wire[`NT_M1:0][31:0] out_a_reg_data,
output wire[`NT_M1:0][31:0] out_b_reg_data,
output wire[`NT_M1:0][31:0] real_a_reg_data,
output wire[`NT_M1:0][31:0] real_b_reg_data,
output wire out_gpr_stall
);
VX_gpr_read_inter VX_gpr_read();
assign VX_gpr_read.rs1 = rs1;
assign VX_gpr_read.rs2 = rs2;
assign VX_gpr_read.warp_num = warp_num;
VX_wb_inter VX_writeback_inter();
assign VX_writeback_inter.write_data = write_data;
assign VX_writeback_inter.rd = rd;
assign VX_writeback_inter.wb = wb;
assign VX_writeback_inter.wb_valid = wb_valid;
assign VX_writeback_inter.wb_warp_num = wb_warp_num;
VX_generic_register #(.N(157)) input_reg
(
.clk (clk),
.reset(0),
.stall(0),
.flush(0),
.in ({rs1 , rs2 , warp_num , write_data , rd , wb , wb_valid , wb_warp_num }),
.out ({VX_gpr_read.rs1, VX_gpr_read.rs2, VX_gpr_read.warp_num, VX_writeback_inter.write_data, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_valid, VX_writeback_inter.wb_warp_num})
);
wire[`NT_M1:0][31:0] out_a_reg_data;
wire[`NT_M1:0][31:0] out_b_reg_data;
VX_generic_register #(.N(256)) output_reg
(
.clk (clk),
.reset(0),
.stall(0),
.flush(0),
.in ({out_a_reg_data , out_b_reg_data}),
.out ({real_a_reg_data, real_b_reg_data})
);
// wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
// wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;

2
rtl/Vortex.v
View file

@ -15,8 +15,6 @@ module Vortex(
output wire out_ebreak
);
// Dcache Interface
VX_dcache_response_inter VX_dcache_rsp();

9
rtl/byte_enabled_simple_dual_port_ram.v
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@ -5,10 +5,10 @@
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input wire[4:0] waddr, raddr,
input wire[4:0] waddr, raddr1, raddr2,
input wire[`NT_M1:0] be,
input wire[`NT_M1:0][31:0] wdata,
output reg[`NT_M1:0][31:0] q
output reg[`NT_M1:0][31:0] q1, q2
);
// Thread Byte Bit
@ -26,8 +26,7 @@ module byte_enabled_simple_dual_port_ram
end
always_ff@(negedge clk) begin
q <= GPR[raddr];
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
endmodule

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5432
rtl/obj_dir/VVortex.cpp
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30
rtl/obj_dir/VVortex.h
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@ -186,23 +186,15 @@ VL_MODULE(VVortex) {
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__in_valid[4],0,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
};
struct {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
};
// LOCAL VARIABLES
@ -222,22 +214,6 @@ VL_MODULE(VVortex) {
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_b_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_a_reg_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);

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rtl/obj_dir/VVortex__verFiles.dat
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@ -11,13 +11,13 @@ S 5559 897862 1568179536 0 1568179536 0 "VX_fetch.v
S 6148 897415 1568177866 0 1568177866 0 "VX_forwarding.v"
S 2701 897416 1568177866 0 1568177866 0 "VX_front_end.v"
S 399 897417 1568177866 0 1568177866 0 "VX_generic_register.v"
S 1835 897418 1568177866 0 1568177866 0 "VX_gpr.v"
S 2222 900429 1568225464 0 1568225464 0 "VX_gpr.v"
S 5323 897420 1568177866 0 1568177866 0 "VX_gpr_wrapper.v"
S 2584 897421 1568177866 0 1568177866 0 "VX_memory.v"
S 1901 899072 1568179744 0 1568179744 0 "VX_warp.v"
S 1597 897426 1568177868 0 1568177868 0 "VX_writeback.v"
S 4392 897427 1568177868 0 1568177868 0 "Vortex.v"
S 821 897428 1568177868 0 1568177868 0 "byte_enabled_simple_dual_port_ram.v"
S 4390 900095 1568217580 0 1568217580 0 "Vortex.v"
S 834 900358 1568227970 0 1568227970 0 "byte_enabled_simple_dual_port_ram.v"
S 1676 897412 1568177866 0 1568177866 0 "interfaces//../VX_define.v"
S 227 897429 1568177888 0 1568177888 0 "interfaces//VX_branch_response_inter.v"
S 212 897430 1568177888 0 1568177888 0 "interfaces//VX_csr_write_request_inter.v"
@ -42,32 +42,32 @@ S 557 897450 1568177890 0 1568177890 0 "interfaces
S 348 897451 1568177890 0 1568177890 0 "interfaces//VX_mw_wb_inter.v"
S 297 897452 1568177890 0 1568177890 0 "interfaces//VX_warp_ctl_inter.v"
S 273 897453 1568177890 0 1568177890 0 "interfaces//VX_wb_inter.v"
T 1307652 897708 1568180202 0 1568180202 0 "obj_dir/VVortex.cpp"
T 24070 897706 1568180202 0 1568180202 0 "obj_dir/VVortex.h"
T 1791 897807 1568180202 0 1568180202 0 "obj_dir/VVortex.mk"
T 914 897795 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 897794 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 897791 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 897790 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 897789 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 897788 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 914 897793 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1031 897792 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 897803 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 897802 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 897799 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 897798 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 897801 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 897800 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 897797 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 897796 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 825 897805 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 897804 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 897705 1568180202 0 1568180202 0 "obj_dir/VVortex__Syms.cpp"
T 1855 897704 1568180202 0 1568180202 0 "obj_dir/VVortex__Syms.h"
T 2113 897808 1568180202 0 1568180202 0 "obj_dir/VVortex__ver.d"
T 0 0 1568180202 0 1568180202 0 "obj_dir/VVortex__verFiles.dat"
T 1530 897806 1568180202 0 1568180202 0 "obj_dir/VVortex_classes.mk"
T 947185 900346 1568227976 0 1568227976 0 "obj_dir/VVortex.cpp"
T 20294 900344 1568227976 0 1568227976 0 "obj_dir/VVortex.h"
T 1791 900898 1568227976 0 1568227976 0 "obj_dir/VVortex.mk"
T 914 900886 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 900885 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 900882 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 900855 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 900793 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 900782 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 914 900884 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1031 900883 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 900894 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 900893 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 900890 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 900889 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 900892 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 900891 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 900888 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 900887 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 825 900896 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 900895 1568227976 0 1568227976 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 900343 1568227976 0 1568227976 0 "obj_dir/VVortex__Syms.cpp"
T 1855 900342 1568227976 0 1568227976 0 "obj_dir/VVortex__Syms.h"
T 2113 900899 1568227976 0 1568227976 0 "obj_dir/VVortex__ver.d"
T 0 0 1568227976 0 1568227976 0 "obj_dir/VVortex__verFiles.dat"
T 1530 900897 1568227976 0 1568227976 0 "obj_dir/VVortex_classes.mk"
S 1884 897454 1568177900 0 1568177900 0 "pipe_regs//VX_d_e_reg.v"
S 1538 897455 1568177900 0 1568177900 0 "pipe_regs//VX_e_m_reg.v"
S 751 897456 1568177900 0 1568177900 0 "pipe_regs//VX_f_d_reg.v"

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rtl/results.txt
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@ -3,5 +3,5 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00015
# time to simulate: 2.15924e-314 milliseconds
# time to simulate: 2.22904e-314 milliseconds
# GRADE: Failed on test: 4294967295

2
rtl/test_bench.h
View file

@ -353,7 +353,7 @@ bool Vortex::simulate(std::string file_to_simulate)
// unsigned cycles;
counter = 0;
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles <= 30)
// while (this->stats_total_cycles < 10)
{
// std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";