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dispatch refactoring
This commit is contained in:
Blaise Tine
parent
5423958366
commit
fe862f64b1
7 changed files with 69 additions and 87 deletions
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@ -1,6 +1,6 @@
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`include "VX_define.vh"
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module VX_instr_demux (
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module VX_dispatch (
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input wire clk,
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input wire reset,
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@ -23,56 +23,60 @@ module VX_issue #(
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`endif
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VX_gpu_req_if.master gpu_req_if
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);
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VX_ibuffer_if ibuffer_if();
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VX_gpr_rsp_if gpr_rsp_if();
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VX_gpr_req_if gpr_req_if();
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assign gpr_req_if.wid = ibuffer_if.wid;
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assign gpr_req_if.rs1 = ibuffer_if.rs1;
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assign gpr_req_if.rs2 = ibuffer_if.rs2;
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assign gpr_req_if.rs3 = ibuffer_if.rs3;
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VX_ibuffer_if ibuffer_if();
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VX_gpr_req_if gpr_req_if();
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VX_gpr_rsp_if gpr_rsp_if();
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VX_writeback_if sboard_wb_if();
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assign sboard_wb_if.valid = writeback_if.valid;
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assign sboard_wb_if.wid = writeback_if.wid;
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assign sboard_wb_if.PC = writeback_if.PC;
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assign sboard_wb_if.rd = writeback_if.rd;
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assign sboard_wb_if.eop = writeback_if.eop;
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assign sboard_wb_if.ready = writeback_if.ready;
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VX_ibuffer_if sboard_ib_if();
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assign sboard_ib_if.valid = ibuffer_if.valid && idmux_ib_if.ready;
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assign sboard_ib_if.wid = ibuffer_if.wid;
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assign sboard_ib_if.PC = ibuffer_if.PC;
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assign sboard_ib_if.wb = ibuffer_if.wb;
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assign sboard_ib_if.rd = ibuffer_if.rd;
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assign sboard_ib_if.rd_n = ibuffer_if.rd_n;
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assign sboard_ib_if.rs1_n = ibuffer_if.rs1_n;
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assign sboard_ib_if.rs2_n = ibuffer_if.rs2_n;
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assign sboard_ib_if.rs3_n = ibuffer_if.rs3_n;
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assign sboard_ib_if.wid_n = ibuffer_if.wid_n;
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VX_ibuffer_if scoreboard_if();
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VX_ibuffer_if dispatch_if();
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VX_ibuffer_if idmux_ib_if();
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assign idmux_ib_if.valid = ibuffer_if.valid && sboard_ib_if.ready;
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assign idmux_ib_if.wid = ibuffer_if.wid;
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assign idmux_ib_if.tmask = ibuffer_if.tmask;
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assign idmux_ib_if.PC = ibuffer_if.PC;
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assign idmux_ib_if.ex_type = ibuffer_if.ex_type;
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assign idmux_ib_if.op_type = ibuffer_if.op_type;
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assign idmux_ib_if.op_mod = ibuffer_if.op_mod;
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assign idmux_ib_if.wb = ibuffer_if.wb;
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assign idmux_ib_if.rd = ibuffer_if.rd;
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assign idmux_ib_if.rs1 = ibuffer_if.rs1;
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assign idmux_ib_if.imm = ibuffer_if.imm;
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assign idmux_ib_if.use_PC = ibuffer_if.use_PC;
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assign idmux_ib_if.use_imm = ibuffer_if.use_imm;
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// GPR request interface
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assign gpr_req_if.wid = ibuffer_if.wid;
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assign gpr_req_if.rs1 = ibuffer_if.rs1;
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assign gpr_req_if.rs2 = ibuffer_if.rs2;
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assign gpr_req_if.rs3 = ibuffer_if.rs3;
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// scoreboard writeback interface
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assign sboard_wb_if.valid = writeback_if.valid;
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assign sboard_wb_if.wid = writeback_if.wid;
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assign sboard_wb_if.PC = writeback_if.PC;
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assign sboard_wb_if.rd = writeback_if.rd;
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assign sboard_wb_if.eop = writeback_if.eop;
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// scoreboard interface
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assign scoreboard_if.valid = ibuffer_if.valid && dispatch_if.ready;
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assign scoreboard_if.wid = ibuffer_if.wid;
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assign scoreboard_if.PC = ibuffer_if.PC;
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assign scoreboard_if.wb = ibuffer_if.wb;
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assign scoreboard_if.rd = ibuffer_if.rd;
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assign scoreboard_if.rd_n = ibuffer_if.rd_n;
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assign scoreboard_if.rs1_n = ibuffer_if.rs1_n;
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assign scoreboard_if.rs2_n = ibuffer_if.rs2_n;
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assign scoreboard_if.rs3_n = ibuffer_if.rs3_n;
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assign scoreboard_if.wid_n = ibuffer_if.wid_n;
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// dispatch interface
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assign dispatch_if.valid = ibuffer_if.valid && scoreboard_if.ready;
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assign dispatch_if.wid = ibuffer_if.wid;
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assign dispatch_if.tmask = ibuffer_if.tmask;
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assign dispatch_if.PC = ibuffer_if.PC;
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assign dispatch_if.ex_type = ibuffer_if.ex_type;
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assign dispatch_if.op_type = ibuffer_if.op_type;
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assign dispatch_if.op_mod = ibuffer_if.op_mod;
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assign dispatch_if.wb = ibuffer_if.wb;
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assign dispatch_if.rd = ibuffer_if.rd;
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assign dispatch_if.rs1 = ibuffer_if.rs1;
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assign dispatch_if.imm = ibuffer_if.imm;
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assign dispatch_if.use_PC = ibuffer_if.use_PC;
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assign dispatch_if.use_imm = ibuffer_if.use_imm;
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// issue the instruction
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assign ibuffer_if.ready = sboard_ib_if.ready && idmux_ib_if.ready;
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assign ibuffer_if.ready = scoreboard_if.ready && dispatch_if.ready;
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`RESET_RELAY (ibuf_reset);
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`RESET_RELAY (scoreboard_reset);
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`RESET_RELAY (gpr_reset);
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`RESET_RELAY (demux_reset);
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`RESET_RELAY (dispatch_reset);
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VX_ibuffer #(
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.CORE_ID(CORE_ID)
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@ -87,9 +91,9 @@ module VX_issue #(
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.CORE_ID(CORE_ID)
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) scoreboard (
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.clk (clk),
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.reset (reset),
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.ibuffer_if (sboard_ib_if),
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.writeback_if(sboard_wb_if)
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.reset (scoreboard_reset),
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.writeback_if(sboard_wb_if),
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.ibuffer_if (scoreboard_if)
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);
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VX_gpr_stage #(
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@ -102,10 +106,10 @@ module VX_issue #(
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.gpr_rsp_if (gpr_rsp_if)
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);
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VX_instr_demux instr_demux (
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VX_dispatch dispatch (
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.clk (clk),
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.reset (demux_reset),
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.ibuffer_if (idmux_ib_if),
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.reset (dispatch_reset),
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.ibuffer_if (dispatch_if),
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.gpr_rsp_if (gpr_rsp_if),
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.alu_req_if (alu_req_if),
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.lsu_req_if (lsu_req_if),
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@ -131,11 +135,11 @@ module VX_issue #(
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`SCOPE_ASSIGN (issue_imm, ibuffer_if.imm);
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`SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC);
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`SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm);
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`SCOPE_ASSIGN (scoreboard_delay, !sboard_wb_if.ready);
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`SCOPE_ASSIGN (execute_delay, !idmux_ib_if.ready);
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`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
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`SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data);
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`SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data);
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`SCOPE_ASSIGN (scoreboard_delay, !scoreboard_if.ready);
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`SCOPE_ASSIGN (dispatch_delay, !dispatch_if.ready);
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`SCOPE_ASSIGN (gpr_rs1, gpr_rsp_if.rs1_data);
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`SCOPE_ASSIGN (gpr_rs2, gpr_rsp_if.rs2_data);
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`SCOPE_ASSIGN (gpr_rs3, gpr_rsp_if.rs3_data);
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`SCOPE_ASSIGN (writeback_valid, writeback_if.valid);
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`SCOPE_ASSIGN (writeback_tmask, writeback_if.tmask);
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`SCOPE_ASSIGN (writeback_wid, writeback_if.wid);
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@ -170,7 +174,7 @@ module VX_issue #(
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if (decode_if.valid & !decode_if.ready) begin
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perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1;
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end
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if (ibuffer_if.valid & !sboard_wb_if.ready) begin
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if (scoreboard_if.valid & !scoreboard_if.ready) begin
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perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1;
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end
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if (alu_req_if.valid & !alu_req_if.ready) begin
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@ -6,8 +6,8 @@ module VX_scoreboard #(
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input wire clk,
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input wire reset,
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VX_ibuffer_if.scoreboard ibuffer_if,
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VX_writeback_if.scoreboard writeback_if
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VX_ibuffer_if.slave ibuffer_if,
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VX_writeback_if.slave writeback_if
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);
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reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
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@ -53,6 +53,7 @@ module VX_scoreboard #(
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reg [31:0] deadlock_ctr;
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wire [31:0] deadlock_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
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always @(posedge clk) begin
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if (reset) begin
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deadlock_ctr <= 0;
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@ -76,20 +76,6 @@ interface VX_ibuffer_if ();
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input wid_n,
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output ready
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);
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modport scoreboard (
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input valid,
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input wid,
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input PC,
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input wb,
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input rd,
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input rd_n,
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input rs1_n,
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input rs2_n,
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input rs3_n,
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input wid_n,
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output ready
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);
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endinterface
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@ -36,15 +36,6 @@ interface VX_writeback_if ();
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output ready
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);
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modport scoreboard (
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input valid,
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input wid,
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input PC,
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input rd,
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input eop,
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output ready
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);
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endinterface
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`endif
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@ -194,9 +194,9 @@
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"issue_imm": 32,
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"issue_use_pc": 1,
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"issue_use_imm": 1,
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"gpr_rsp_a":"`NUM_THREADS * 32",
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"gpr_rsp_b":"`NUM_THREADS * 32",
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"gpr_rsp_c":"`NUM_THREADS * 32",
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"gpr_rs1":"`NUM_THREADS * 32",
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"gpr_rs2":"`NUM_THREADS * 32",
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"gpr_rs3":"`NUM_THREADS * 32",
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"?writeback_valid": 1,
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"writeback_wid":"`NW_BITS",
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"writeback_pc": 32,
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@ -205,7 +205,7 @@
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"writeback_data":"`NUM_THREADS * 32",
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"writeback_eop": 1,
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"!scoreboard_delay": 1,
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"!execute_delay": 1
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"!dispatch_delay": 1
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},
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"afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank": {
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"?valid_st0": 1,
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@ -86,12 +86,12 @@ VL_FLAGS += -D$(FPU_CORE)
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PROJECT = libopae-c-vlsim
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all: shared
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all: $(PROJECT).so
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vortex_afu.h : $(RTL_DIR)/afu/vortex_afu.vh
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$(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/afu/vortex_afu.vh -o vortex_afu.h
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shared: $(SRCS) vortex_afu.h
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$(PROJECT).so: $(SRCS) vortex_afu.h
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verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT).so
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static: $(SRCS) vortex_afu.h
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