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critical path optimizations
This commit is contained in:
Blaise Tine
parent
73d102afed
commit
feca2db24e
4 changed files with 49 additions and 50 deletions
12
hw/rtl/cache/VX_nc_bypass.v
vendored
12
hw/rtl/cache/VX_nc_bypass.v
vendored
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@ -107,6 +107,7 @@ module VX_nc_bypass #(
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wire [NUM_REQS-1:0] core_req_valid_in_nc;
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wire [NUM_REQS-1:0] core_req_nc_tids;
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wire [`UP(CORE_REQ_TIDW)-1:0] core_req_nc_tid;
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wire [NUM_REQS-1:0] core_req_nc_sel;
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wire core_req_nc_valid;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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@ -115,12 +116,13 @@ module VX_nc_bypass #(
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assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_tids;
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VX_lzc #(
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VX_priority_encoder #(
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.N (NUM_REQS)
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) core_req_sel (
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.in_i (core_req_valid_in_nc),
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.cnt_o (core_req_nc_tid),
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.valid_o (core_req_nc_valid)
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.data_in (core_req_valid_in_nc),
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.index (core_req_nc_tid),
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.onehot (core_req_nc_sel),
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.valid_out (core_req_nc_valid)
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);
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assign core_req_valid_out = core_req_valid_in & ~core_req_nc_tids;
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@ -143,7 +145,7 @@ module VX_nc_bypass #(
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if (NUM_REQS > 1) begin
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_ready_in[i] = core_req_valid_in_nc[i] ?
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(~mem_req_valid_in && mem_req_ready_out && (core_req_nc_tid == i)) : core_req_ready_out[i];
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(~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i]) : core_req_ready_out[i];
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end
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end else begin
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assign core_req_ready_in = core_req_valid_in_nc ? (~mem_req_valid_in && mem_req_ready_out) : core_req_ready_out;
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@ -180,39 +180,35 @@ module VX_fp_cvt #(
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wire [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s1;
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wire [LANES-1:0] of_before_round_s1;
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for (genvar i = 0; i < LANES; ++i) begin
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wire [INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination
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for (genvar i = 0; i < LANES; ++i) begin
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reg [2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift
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reg [SHAMT_BITS-1:0] denorm_shamt; // shift amount for denormalization
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reg [INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments
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reg of_before_round;
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// Rebias the exponent
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assign destination_exp = input_exp_s1[i] + EXP_BIAS;
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always @(*) begin
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`IGNORE_WARNINGS_BEGIN
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// Default assignment
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final_exp = destination_exp; // take exponent as is, only look at lower bits
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preshift_mant = {input_mant_s1[i], 33'b0}; // Place mantissa to the left of the shifter
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final_exp = input_exp_s1[i] + EXP_BIAS; // take exponent as is, only look at lower bits
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preshift_mant = {input_mant_s1[i], 33'b0}; // Place mantissa to the left of the shifter
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denorm_shamt = 0; // right of mantissa
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of_before_round = 1'b0;
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// Handle INT casts
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if (is_itof_s1) begin
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if ($signed(destination_exp) >= $signed(2**EXP_BITS-1)) begin
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if ($signed(input_exp_s1[i]) >= $signed(2**EXP_BITS-1-EXP_BIAS)) begin
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// Overflow or infinities (for proper rounding)
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final_exp = (2**EXP_BITS-2); // largest normal value
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preshift_mant = ~0; // largest normal value and RS bits set
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of_before_round = 1'b1;
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end else if ($signed(destination_exp) < $signed(-MAN_BITS)) begin
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end else if ($signed(input_exp_s1[i]) < $signed(-MAN_BITS-EXP_BIAS)) begin
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// Limit the shift to retain sticky bits
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final_exp = 0; // denormal result
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denorm_shamt = denorm_shamt + (2 + MAN_BITS); // to sticky
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end else if ($signed(destination_exp) < $signed(1)) begin
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denorm_shamt = (2 + MAN_BITS); // to sticky
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end else if ($signed(input_exp_s1[i]) < $signed(1-EXP_BIAS)) begin
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// Denormalize underflowing values
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final_exp = 0; // denormal result
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denorm_shamt = denorm_shamt + 1 - destination_exp; // adjust right shifting
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denorm_shamt = (1-EXP_BIAS) - input_exp_s1[i]; // adjust right shifting
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end
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end else begin
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if ($signed(input_exp_s1[i]) >= $signed((MAX_INT_WIDTH-1) + unsigned_s1)) begin
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@ -221,7 +217,7 @@ module VX_fp_cvt #(
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of_before_round = 1'b1;
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end else if ($signed(input_exp_s1[i]) < $signed(-1)) begin
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// underflow
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denorm_shamt = MAX_INT_WIDTH + 1; // all bits go to the sticky
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denorm_shamt = MAX_INT_WIDTH+1; // all bits go to the sticky
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end else begin
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// By default right shift mantissa to be an integer
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denorm_shamt = (MAX_INT_WIDTH-1) - input_exp_s1[i];
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@ -46,17 +46,17 @@ module VX_priority_encoder #(
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.data_out (scan_lo)
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);
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VX_lzc #(
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.N (N)
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) lzc (
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.in_i (reversed),
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.cnt_o (index),
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`UNUSED_PIN (valid_o)
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);
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assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
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assign valid_out = scan_lo[N-1];
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VX_onehot_encoder #(
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.N (N)
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) onehot_encoder (
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.data_in (onehot),
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.data_out (index),
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`UNUSED_PIN (valid_out)
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);
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end else if (MODEL == 2) begin
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`IGNORE_WARNINGS_BEGIN
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@ -66,30 +66,26 @@ module VX_priority_encoder #(
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assign higher_pri_regs[0] = 1'b0;
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assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
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VX_onehot_encoder #(
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VX_lzc #(
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.N (N)
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) onehot_encoder (
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.data_in (onehot),
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.data_out (index),
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`UNUSED_PIN (valid_out)
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) lzc (
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.in_i (reversed),
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.cnt_o (index),
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.valid_o (valid_out)
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);
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assign valid_out = (| reversed);
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end else if (MODEL == 3) begin
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assign onehot = reversed & ~(reversed-1);
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VX_onehot_encoder #(
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VX_lzc #(
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.N (N)
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) onehot_encoder (
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.data_in (onehot),
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.data_out (index),
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`UNUSED_PIN (valid_out)
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) lzc (
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.in_i (reversed),
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.cnt_o (index),
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.valid_o (valid_out)
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);
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assign valid_out = (| reversed);
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end else begin
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reg [LN-1:0] index_r;
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@ -25,6 +25,7 @@ module VX_stream_arbiter #(
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wire sel_valid;
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wire sel_ready;
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wire [LOG_NUM_REQS-1:0] sel_index;
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wire [NUM_REQS-1:0] sel_onehot;
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wire [NUM_REQS-1:0] valid_in_any;
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wire [LANES-1:0] ready_in_sel;
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@ -42,13 +43,17 @@ module VX_stream_arbiter #(
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end
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if (TYPE == "P") begin
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`UNUSED_VAR (sel_ready)
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VX_lzc #(
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.N (NUM_REQS)
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VX_fixed_arbiter #(
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.NUM_REQS (NUM_REQS),
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.LOCK_ENABLE (LOCK_ENABLE)
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) sel_arb (
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.in_i (valid_in_any),
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.cnt_o (sel_index),
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.valid_o (sel_valid)
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.clk (clk),
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.reset (reset),
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.requests (valid_in_any),
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_index (sel_index),
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.grant_onehot (sel_onehot)
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);
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end else if (TYPE == "R") begin
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VX_rr_arbiter #(
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@ -61,7 +66,7 @@ module VX_stream_arbiter #(
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_index (sel_index),
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`UNUSED_PIN (grant_onehot)
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.grant_onehot (sel_onehot)
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);
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end else if (TYPE == "F") begin
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VX_fair_arbiter #(
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@ -74,7 +79,7 @@ module VX_stream_arbiter #(
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_index (sel_index),
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`UNUSED_PIN (grant_onehot)
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.grant_onehot (sel_onehot)
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);
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end else if (TYPE == "M") begin
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VX_matrix_arbiter #(
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@ -87,7 +92,7 @@ module VX_stream_arbiter #(
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.enable (sel_ready),
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.grant_valid (sel_valid),
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.grant_index (sel_index),
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`UNUSED_PIN (grant_onehot)
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.grant_onehot (sel_onehot)
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);
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end else begin
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$error ("invalid parameter");
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@ -109,7 +114,7 @@ module VX_stream_arbiter #(
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end
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign ready_in[i] = ready_in_sel & {LANES{(sel_index == LOG_NUM_REQS'(i))}};
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assign ready_in[i] = ready_in_sel & {LANES{sel_onehot[i]}};
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end
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for (genvar i = 0; i < LANES; ++i) begin
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