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Fix few more tests

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This commit is contained in:
Shashank Holla 2023-03-31 09:17:54 -04:00 • committed by Blaise Tine
parent ada353e394
commit ff24275048
2 changed files with 15 additions and 15 deletions
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12
hw/rtl/core/VX_decode.sv
View file

@ -53,12 +53,12 @@ module VX_decode #(
wire [4:0] rs2 = instr[24:20];
wire [4:0] rs3 = instr[31:27];
wire [19:0] upper_imm = {func7, rs2, rs1, func3};
// wire [11:0] alu_imm = (func3 == 3'b001) ? {{7{1'b0}}, instr[25:20]} : ((func3[0] && ~func3[1]) ? {{7{1'b0}}, rs2} : u_12);
wire [11:0] alu_imm = (func3 == 3'b001) ? {{6{1'b0}}, instr[25:20]} : ((func3[0] && ~func3[1]) ? {{7{1'b0}}, rs2} : u_12);
wire [11:0] s_imm = {func7, rd};
wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
wire [19:0] upper_imm = {func7, rs2, rs1, func3};
wire [11:0] alu_imm = (func3[0] && ~func3[1]) ? {{6{1'b0}}, instr[25:20]} : u_12;
wire [11:0] s_imm = {func7, rd};
wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
`UNUSED_VAR (rs3)

18
hw/rtl/core/VX_lsu_unit.sv
View file

@ -11,7 +11,7 @@ module VX_lsu_unit #(
) (
`SCOPE_IO_DECL
input wire clk,
input wire clk,
input wire reset,
// Dcache interface
@ -139,15 +139,15 @@ module VX_lsu_unit #(
end
// data formatting
wire[`NUM_THREADS-1:0][REQ_ASHIFT-1:0] req_align_X1;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire [REQ_ASHIFT-1:0] req_align_X1;
`ifdef MODE_32_BIT
assign req_align_X1 = {req_align[i][1], 1'b1};
assign req_align_X1[i] = {req_align[i][1], 1'b1};
`endif
`ifdef MODE_64_BIT
// TODO: VARUN TO CHECK
assign req_align_X1 = {1'b0, req_align[i][1:0]};
assign req_align_X1[i] = {req_align[i][1:0], 1'b1};
`endif
always @(*) begin
mem_req_byteen[i] = {DCACHE_WORD_SIZE{lsu_req_if.wb}};
@ -155,13 +155,13 @@ module VX_lsu_unit #(
0: mem_req_byteen[i][req_align[i]] = 1;
1: begin // half (16 bit)
mem_req_byteen[i][req_align[i]] = 1;
mem_req_byteen[i][req_align_X1] = 1;
mem_req_byteen[i][req_align_X1[i]] = 1;
end
2: begin // word (32 bit)
mem_req_byteen[i][req_align[i]] = 1;
mem_req_byteen[i][req_align_X1] = 1;
mem_req_byteen[i][req_align_X1+1] = 1;
mem_req_byteen[i][req_align_X1+2] = 1;
mem_req_byteen[i][req_align_X1[i]] = 1;
mem_req_byteen[i][req_align_X1[i]+1] = 1;
mem_req_byteen[i][req_align_X1[i]+2] = 1;
end
default : mem_req_byteen[i] = {DCACHE_WORD_SIZE{1'b1}}; // double (64 bit)
endcase