12 commits

Author	SHA1	Message	Date
Udit Subramanya	e73e1c2bb3	update xilinx fpga steps with environment variable steps	2024-11-01 13:56:01 -04:00
Udit Subramanya	d475e9d201	remove duplicate block	2024-10-25 12:59:24 -04:00
Udit Subramanya	24d018b4c9	documentation updates	2024-10-23 05:18:53 -04:00
Udit Subramanya	8fdca0e52a	correct vitis env	2024-10-21 15:38:53 -04:00
Udit Subramanya	d584e7bac1	intermediate docs update	2024-10-21 13:28:57 -04:00
Udit Subramanya	208c5b3804	reorg docs	2024-10-04 08:56:49 -04:00
Udit Subramanya	dd16d70515	contributing and fpga docs	2024-10-03 17:29:21 -04:00
Blaise Tine	0aaf010a62	doc update	2024-05-17 13:30:26 -07:00
Blaise Tine	62cdd8e993	minor update	2023-11-11 15:49:39 -08:00
Blaise Tine	c1e168fdbe	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update	2023-11-10 02:47:05 -08:00
Blaise Tine	009e897cab	minor update	2021-10-19 17:12:40 -04:00
Blaise Tine	956f3d1880	docs update	2021-10-19 16:32:31 -04:00

Renamed from doc/fpga_setup.md (Browse further)