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3401 commits 27 branches 9 tags 1.6 GiB
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9 commits

Author SHA1 Message Date
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bfbe642170 adding RTL uuigen 2024-09-07 01:36:17 -07:00
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deee7cd8b0 fixed tracing support for xilinx simulation 2024-06-18 23:11:58 -07:00
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99eaaf6189 uuid_gen cleanup 2024-06-08 01:57:38 -07:00
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d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
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b8682f56ac softfloat library integration 2021-10-10 13:20:50 -07:00
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a60bfc5e01 extending tracing feature for advanced debugging 2021-08-15 05:10:46 -07:00
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c2b3aaa7d1 enabling delayed tracing 2021-08-12 20:05:43 -07:00
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c331da5ff7 adding fast DPI implemntation of imul and idiv 2021-06-22 09:02:41 -07:00
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2b8435471a speeding up simulation using dedicated full dpi-based FPU core 2021-01-06 18:44:06 -08:00