Commit graph

12 commits

Author SHA1 Message Date
tinebp
704f525fd6 memory mem_coalescer miss perf counter
RTL perf counters refactoring
2024-12-26 08:00:36 -08:00
tinebp
3ace9bbeda minor updates
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2024-12-04 06:00:19 -08:00
donghanyuan
1a9a04ac76 replace local static allocator to global static
Ensure MemoryPool construct before SimPlatform,
thus MemoryPool destruct after SimPlatform.

Avoid use-after-free issue clearing events_ of SimPlatform
after SimPortEvent's allocator is destructed.
2024-08-13 18:13:41 +08:00
Blaise Tine
ff6f33acff simx refactoring: simobject::push(), instr_trace, FUtype, pending_instrs_ 2024-03-11 15:39:49 -07:00
Blaise Tine
d47cccc157 Vortex 2.0 changes:
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
5825b7c15a dram simulator fix 2021-12-07 22:44:06 -05:00
Blaise Tine
b741807f8c using ramulator dram simulator 2021-12-06 01:22:45 -05:00
Blaise Tine
41d7e6c63a cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes 2021-11-30 07:08:15 -05:00
Blaise Tine
18762dffce fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id, 2021-11-24 00:00:17 -05:00
Blaise Tine
27a65fdee7 driver refactoring 2021-11-14 09:05:15 -05:00
Blaise Tine
808bddb586 simx timing simulation refactoring 2021-11-14 08:52:34 -05:00
Blaise Tine
c2721fd545 SimX timing simulation 2021-11-13 01:41:12 -05:00