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3339 commits 27 branches 9 tags 1.6 GiB
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11 commits

Author SHA1 Message Date
MichaelJSr
073e0ddd10 Adds the riscv vector extension into simx 
Added vector regression test to ci.yml
 2024-11-27 23:22:22 -08:00
Blaise Tine
d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
Blaise Tine
140124b423 additional bug fixes 2022-02-05 07:42:50 -05:00
Blaise Tine
5fbace9fa0 fixed several bugs and refactor memory access 2022-02-04 17:50:19 -05:00
Blaise Tine
cf2a0a5f39 code refactoring 2022-02-04 00:07:24 -05:00
Santosh Srivatsan
836c777680 XLEN parameterization for simx 2022-02-03 15:19:31 -05:00
Santosh Srivatsan
91c22a2592 Fixed some riscv-tests 2022-01-22 12:54:10 -05:00
Santosh Srivatsan
b1e82223ee Renamed rv_f* functions to rvf*_s to follow the naming convention between single and double precision floating point 2021-12-13 20:37:29 -05:00
Santosh Raghav Srivatsan
bde789b320 Added support for RV32D and RV64D instructions 2021-12-10 16:30:24 -05:00
Santosh Raghav Srivatsan
e6eda67d0c Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension 2021-12-06 18:55:13 -05:00
Blaise Tine
48b2238a1f adding rvfloats library 2021-10-10 13:26:11 -07:00