9 commits

Author	SHA1	Message	Date
MichaelJSr	929ef1b6e2	Remove unused EXTV code, clean up code, pragma once around vpu.h	2025-01-13 16:45:13 -08:00
MichaelJSr	073e0ddd10	Adds the riscv vector extension into simx ... Added vector regression test to ci.yml	2024-11-27 23:22:22 -08:00
Jaewon Lee	4a606061d2	Merge branch 'develop' into tensor-core	2024-09-30 16:48:47 -04:00
Blaise Tine	3efced37c5	trace INSTANCE_ID refactoring	2024-07-09 13:33:17 -07:00
Nayan Sivakumar Nair	a378aed67c	Moved tc_num, tc_size param to makefile args	2024-06-21 22:23:24 -04:00
Varsha Singhania	99c6a1af5a	Tensor cores in Vortex	2024-06-17 04:28:51 -04:00
Blaise Tine	6c56edf65d	minor update	2024-06-04 14:28:30 -07:00
Blaise Tine	c7a81d1493	adding sockets support to simx and cache subsystem refactoring ... minor update minor update minor updates	2023-12-20 15:16:12 -08:00
Blaise Tine	d47cccc157	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes	2023-10-19 20:51:22 -07:00