17 commits

Author	SHA1	Message	Date
Blaise Tine	9143c19be3	simx perf counters updates	2022-08-02 18:53:15 -07:00
Blaise Tine	d091c7cd12	adding per-cluster l1 cache support to simx	2022-06-28 23:01:19 -04:00
Blaise Tine	20b1a4de34	multiple rasterizer units support	2022-05-25 11:15:55 -04:00
Blaise Tine	83f0e6bdf2	minor update	2022-04-27 01:43:30 -04:00
Blaise Tine	ee8a128885	simx graphics timing simulation	2022-04-15 07:49:04 -04:00
Blaise Tine	5bde690079	fixed l2_enable, l3_enable, sm_enable configurations	2022-03-20 19:30:03 -04:00
Blaise Tine	45150919e3	rasterizer simulator updates	2022-03-09 02:17:45 -05:00
Blaise Tine	d1e9b3283c	simx files refactoring	2022-03-07 06:39:15 -05:00
Blaise Tine	4d51d15ab9	simx rasterizer & render output implementation	2022-03-05 20:59:11 -05:00
Blaise Tine	302387a2cf	moved global csrs to device configuration registers (DCRs) to resolve namespace conflict & added vx_interp & draw3d kernel update	2022-03-02 12:22:18 -05:00
Blaise Tine	f3075a0d3f	added global csrs support & moved raster and rop outside core	2022-02-23 18:43:52 -05:00
Blaise Tine	38e1f42e40	smx codebase refactoring	2022-02-17 15:51:36 -05:00
Blaise Tine	5825b7c15a	dram simulator fix	2021-12-07 22:44:06 -05:00
Blaise Tine	b741807f8c	using ramulator dram simulator	2021-12-06 01:22:45 -05:00
Blaise Tine	189cec3ca2	minor update	2021-12-01 10:36:50 -05:00
Blaise Tine	092ff42ab4	simx multicore fix	2021-12-01 00:12:16 -05:00
Blaise Tine	2a7a4df342	simx directory name fix	2021-11-30 07:17:58 -05:00

Renamed from sim/simX/processor.cpp (Browse further)