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113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __FPGA_H__
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#define __FPGA_H__
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#include <stdint.h>
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#include <uuid/uuid.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Copyright (C) 2019, Xilinx Inc - All rights reserved.
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* Xilinx Runtime (XRT) APIs
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*
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* Licensed under the Apache License, Version 2.0 (the "License"). You may
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* not use this file except in compliance with the License. A copy of the
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* License is located at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*/
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/**
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* XCL BO Flags bits layout
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* bits 0 ~ 15: DDR BANK index
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* bits 24 ~ 31: BO flags
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*/
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#define XRT_BO_FLAGS_MEMIDX_MASK (0xFFFFFFUL)
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#define XCL_BO_FLAGS_NONE (0)
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#define XCL_BO_FLAGS_CACHEABLE (1U << 24)
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#define XCL_BO_FLAGS_KERNBUF (1U << 25)
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#define XCL_BO_FLAGS_SGL (1U << 26)
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#define XCL_BO_FLAGS_SVM (1U << 27)
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#define XCL_BO_FLAGS_DEV_ONLY (1U << 28)
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#define XCL_BO_FLAGS_HOST_ONLY (1U << 29)
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#define XCL_BO_FLAGS_P2P (1U << 30)
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#define XCL_BO_FLAGS_EXECBUF (1U << 31)
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#define XRT_BO_FLAGS_NONE XCL_BO_FLAGS_NONE
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#define XRT_BO_FLAGS_CACHEABLE XCL_BO_FLAGS_CACHEABLE
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#define XRT_BO_FLAGS_DEV_ONLY XCL_BO_FLAGS_DEV_ONLY
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#define XRT_BO_FLAGS_HOST_ONLY XCL_BO_FLAGS_HOST_ONLY
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#define XRT_BO_FLAGS_P2P XCL_BO_FLAGS_P2P
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#define XRT_BO_FLAGS_SVM XCL_BO_FLAGS_SVM
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enum xclBOSyncDirection {
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XCL_BO_SYNC_BO_TO_DEVICE = 0,
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XCL_BO_SYNC_BO_FROM_DEVICE,
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};
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typedef void *xrtDeviceHandle;
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typedef void *xrtKernelHandle;
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typedef void* xrtXclbinHandle;
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typedef void *xrtBufferHandle;
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typedef uint64_t xrtErrorCode;
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typedef uint64_t xrtBufferFlags;
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typedef uint32_t xrtMemoryGroup;
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typedef uuid_t xuid_t;
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xrtDeviceHandle xrtDeviceOpen(unsigned int index);
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int xrtXclbinGetXSAName(xrtDeviceHandle dhdl, char* name, int size, int* ret_size);
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int xrtDeviceClose(xrtDeviceHandle dhdl);
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int xrtKernelClose(xrtKernelHandle kernelHandle);
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xrtBufferHandle xrtBOAlloc(xrtDeviceHandle dhdl, size_t size, xrtBufferFlags flags, xrtMemoryGroup grp);
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int xrtBOFree(xrtBufferHandle bhdl);
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int xrtBOWrite(xrtBufferHandle bhdl, const void* src, size_t size, size_t offset);
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int xrtBORead(xrtBufferHandle bhdl, void* dst, size_t size, size_t offset);
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int xrtBOSync(xrtBufferHandle bhdl, enum xclBOSyncDirection dir, size_t size, size_t offset);
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int xrtKernelWriteRegister(xrtKernelHandle kernelHandle, uint32_t offset, uint32_t data);
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int xrtKernelReadRegister(xrtKernelHandle kernelHandle, uint32_t offset, uint32_t* data);
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int xrtErrorGetString(xrtDeviceHandle, xrtErrorCode error, char* out, size_t len, size_t* out_len);
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#ifdef __cplusplus
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}
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#endif
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#endif // __FPGA_H__
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