mirror of
https://github.com/vortexgpgpu/vortex.git
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259 lines
8.2 KiB
Systemverilog
259 lines
8.2 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_socket import VX_gpu_pkg::*; #(
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parameter SOCKET_ID = 0,
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parameter `STRING INSTANCE_ID = ""
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) (
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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input sysmem_perf_t sysmem_perf,
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`endif
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// DCRs
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VX_dcr_bus_if.slave dcr_bus_if,
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// Memory
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VX_mem_bus_if.master mem_bus_if [`L1_MEM_PORTS],
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`ifdef GBAR_ENABLE
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// Barrier
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VX_gbar_bus_if.master gbar_bus_if,
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`endif
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// Status
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output wire busy
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);
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`ifdef SCOPE
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localparam scope_core = 0;
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`SCOPE_IO_SWITCH (`SOCKET_SIZE);
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`endif
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if per_core_gbar_bus_if[`SOCKET_SIZE]();
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VX_gbar_arb #(
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.NUM_REQS (`SOCKET_SIZE),
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.OUT_BUF ((`SOCKET_SIZE > 1) ? 2 : 0)
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) gbar_arb (
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.clk (clk),
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.reset (reset),
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.bus_in_if (per_core_gbar_bus_if),
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.bus_out_if (gbar_bus_if)
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);
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`endif
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///////////////////////////////////////////////////////////////////////////
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`ifdef PERF_ENABLE
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cache_perf_t icache_perf, dcache_perf;
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sysmem_perf_t sysmem_perf_tmp;
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always @(*) begin
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sysmem_perf_tmp = sysmem_perf;
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sysmem_perf_tmp.icache = icache_perf;
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sysmem_perf_tmp.dcache = dcache_perf;
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end
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`endif
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///////////////////////////////////////////////////////////////////////////
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_WORD_SIZE),
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.TAG_WIDTH (ICACHE_TAG_WIDTH)
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) per_core_icache_bus_if[`SOCKET_SIZE]();
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VX_mem_bus_if #(
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.DATA_SIZE (ICACHE_LINE_SIZE),
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.TAG_WIDTH (ICACHE_MEM_TAG_WIDTH)
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) icache_mem_bus_if[1]();
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`RESET_RELAY (icache_reset, reset);
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VX_cache_cluster #(
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.INSTANCE_ID (`SFORMATF(("%s-icache", INSTANCE_ID))),
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.NUM_UNITS (`NUM_ICACHES),
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.NUM_INPUTS (`SOCKET_SIZE),
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.TAG_SEL_IDX (0),
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.CACHE_SIZE (`ICACHE_SIZE),
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.LINE_SIZE (ICACHE_LINE_SIZE),
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.NUM_BANKS (1),
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.NUM_WAYS (`ICACHE_NUM_WAYS),
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.WORD_SIZE (ICACHE_WORD_SIZE),
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.NUM_REQS (1),
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.MEM_PORTS (1),
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.CRSQ_SIZE (`ICACHE_CRSQ_SIZE),
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.MSHR_SIZE (`ICACHE_MSHR_SIZE),
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.MRSQ_SIZE (`ICACHE_MRSQ_SIZE),
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.MREQ_SIZE (`ICACHE_MREQ_SIZE),
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.TAG_WIDTH (ICACHE_TAG_WIDTH),
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.FLAGS_WIDTH (0),
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.UUID_WIDTH (`UUID_WIDTH),
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.WRITE_ENABLE (0),
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.REPL_POLICY (`ICACHE_REPL_POLICY),
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.NC_ENABLE (0),
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.CORE_OUT_BUF (3),
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.MEM_OUT_BUF (2)
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) icache (
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`ifdef PERF_ENABLE
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.cache_perf (icache_perf),
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`endif
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.clk (clk),
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.reset (icache_reset),
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.core_bus_if (per_core_icache_bus_if),
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.mem_bus_if (icache_mem_bus_if)
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);
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///////////////////////////////////////////////////////////////////////////
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_TAG_WIDTH)
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) per_core_dcache_bus_if[`SOCKET_SIZE * DCACHE_NUM_REQS]();
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_LINE_SIZE),
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.TAG_WIDTH (DCACHE_MEM_TAG_WIDTH)
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) dcache_mem_bus_if[`L1_MEM_PORTS]();
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`RESET_RELAY (dcache_reset, reset);
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VX_cache_cluster #(
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.INSTANCE_ID (`SFORMATF(("%s-dcache", INSTANCE_ID))),
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.NUM_UNITS (`NUM_DCACHES),
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.NUM_INPUTS (`SOCKET_SIZE),
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.TAG_SEL_IDX (0),
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.CACHE_SIZE (`DCACHE_SIZE),
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.LINE_SIZE (DCACHE_LINE_SIZE),
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.NUM_BANKS (`DCACHE_NUM_BANKS),
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.NUM_WAYS (`DCACHE_NUM_WAYS),
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.WORD_SIZE (DCACHE_WORD_SIZE),
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.NUM_REQS (DCACHE_NUM_REQS),
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.MEM_PORTS (`L1_MEM_PORTS),
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.CRSQ_SIZE (`DCACHE_CRSQ_SIZE),
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.MSHR_SIZE (`DCACHE_MSHR_SIZE),
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.MRSQ_SIZE (`DCACHE_MRSQ_SIZE),
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.MREQ_SIZE (`DCACHE_WRITEBACK ? `DCACHE_MSHR_SIZE : `DCACHE_MREQ_SIZE),
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.TAG_WIDTH (DCACHE_TAG_WIDTH),
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.UUID_WIDTH (`UUID_WIDTH),
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.FLAGS_WIDTH (`MEM_REQ_FLAGS_WIDTH),
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.WRITE_ENABLE (1),
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.WRITEBACK (`DCACHE_WRITEBACK),
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.DIRTY_BYTES (`DCACHE_DIRTYBYTES),
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.REPL_POLICY (`DCACHE_REPL_POLICY),
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.NC_ENABLE (1),
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.CORE_OUT_BUF (3),
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.MEM_OUT_BUF (2)
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) dcache (
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`ifdef PERF_ENABLE
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.cache_perf (dcache_perf),
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`endif
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.clk (clk),
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.reset (dcache_reset),
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.core_bus_if (per_core_dcache_bus_if),
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.mem_bus_if (dcache_mem_bus_if)
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);
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///////////////////////////////////////////////////////////////////////////
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for (genvar i = 0; i < `L1_MEM_PORTS; ++i) begin : g_mem_bus_if
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if (i == 0) begin : g_i0
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VX_mem_bus_if #(
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_TAG_WIDTH)
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) l1_mem_bus_if[2]();
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VX_mem_bus_if #(
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
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) l1_mem_arb_bus_if[1]();
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`ASSIGN_VX_MEM_BUS_IF_EX (l1_mem_bus_if[0], icache_mem_bus_if[0], L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH, `UUID_WIDTH);
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`ASSIGN_VX_MEM_BUS_IF_EX (l1_mem_bus_if[1], dcache_mem_bus_if[0], L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH, `UUID_WIDTH);
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VX_mem_arb #(
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.NUM_INPUTS (2),
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.NUM_OUTPUTS(1),
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_TAG_WIDTH),
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.TAG_SEL_IDX(0),
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.ARBITER ("P"), // prioritize the icache
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.REQ_OUT_BUF(3),
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.RSP_OUT_BUF(3)
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) mem_arb (
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.clk (clk),
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.reset (reset),
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.bus_in_if (l1_mem_bus_if),
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.bus_out_if (l1_mem_arb_bus_if)
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);
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`ASSIGN_VX_MEM_BUS_IF (mem_bus_if[0], l1_mem_arb_bus_if[0]);
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end else begin : g_i
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VX_mem_bus_if #(
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
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) l1_mem_arb_bus_if();
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`ASSIGN_VX_MEM_BUS_IF_EX (l1_mem_arb_bus_if, dcache_mem_bus_if[i], L1_MEM_ARB_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH, `UUID_WIDTH);
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`ASSIGN_VX_MEM_BUS_IF (mem_bus_if[i], l1_mem_arb_bus_if);
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end
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end
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///////////////////////////////////////////////////////////////////////////
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wire [`SOCKET_SIZE-1:0] per_core_busy;
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// Generate all cores
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for (genvar core_id = 0; core_id < `SOCKET_SIZE; ++core_id) begin : g_cores
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`RESET_RELAY (core_reset, reset);
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VX_dcr_bus_if core_dcr_bus_if();
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`BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, 1'b1, (`SOCKET_SIZE > 1))
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VX_core #(
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.CORE_ID ((SOCKET_ID * `SOCKET_SIZE) + core_id),
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.INSTANCE_ID (`SFORMATF(("%s-core%0d", INSTANCE_ID, core_id)))
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) core (
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`SCOPE_IO_BIND (scope_core + core_id)
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.clk (clk),
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.reset (core_reset),
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`ifdef PERF_ENABLE
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.sysmem_perf (sysmem_perf_tmp),
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`endif
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.dcr_bus_if (core_dcr_bus_if),
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.dcache_bus_if (per_core_dcache_bus_if[core_id * DCACHE_NUM_REQS +: DCACHE_NUM_REQS]),
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.icache_bus_if (per_core_icache_bus_if[core_id]),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (per_core_gbar_bus_if[core_id]),
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`endif
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.busy (per_core_busy[core_id])
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);
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end
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`BUFFER_EX(busy, (| per_core_busy), 1'b1, 1, (`SOCKET_SIZE > 1));
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endmodule
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