mirror of
https://github.com/vortexgpgpu/vortex.git
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246 lines
7.6 KiB
C
246 lines
7.6 KiB
C
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The intrinsics implemented use RISC-V assembler pseudo-directives defined here:
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// https://sourceware.org/binutils/docs/as/RISC_002dV_002dFormats.html
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#ifndef __VX_INTRINSICS_H__
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#define __VX_INTRINSICS_H__
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#include <stddef.h>
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#include <stdint.h>
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#include <VX_types.h>
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#if defined(__clang__)
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#define __UNIFORM__ __attribute__((annotate("vortex.uniform")))
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#else
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#define __UNIFORM__
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RISCV_CUSTOM0 0x0B
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#define RISCV_CUSTOM1 0x2B
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#define RISCV_CUSTOM2 0x5B
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#define RISCV_CUSTOM3 0x7B
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#define csr_read(csr) ({ \
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size_t __r; \
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__asm__ __volatile__ ("csrr %0, %1" : "=r" (__r) : "i" (csr) : "memory"); \
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__r; \
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})
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#define csr_write(csr, val) ({ \
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size_t __v = (size_t)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "i" (__v) : "memory"); \
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else \
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__asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "r" (__v) : "memory"); \
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})
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#define csr_swap(csr, val) ({ \
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size_t __r; \
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size_t __v = (size_t)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v) : "memory"); \
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else \
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__asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v) : "memory"); \
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__r; \
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})
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#define csr_read_set(csr, val) ({ \
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size_t __r; \
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size_t __v = (size_t)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v) : "memory"); \
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else \
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__asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v) : "memory"); \
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__r; \
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})
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#define csr_set(csr, val) ({ \
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size_t __v = (size_t)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "i" (__v) : "memory"); \
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else \
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__asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "r" (__v) : "memory"); \
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})
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#define csr_read_clear(csr, val) ({ \
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size_t __r; \
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size_t __v = (size_t)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v) : "memory"); \
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else \
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__asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v) : "memory"); \
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__r; \
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})
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#define csr_clear(csr, val) ({ \
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size_t __v = (size_t)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "i" (__v) : "memory"); \
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else \
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__asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "r" (__v) : "memory"); \
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})
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// Set thread mask
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inline void vx_tmc(int thread_mask) {
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__asm__ volatile (".insn r %0, 0, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(thread_mask));
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}
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// disable all threads in the current warp
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inline void vx_tmc_zero() {
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__asm__ volatile (".insn r %0, 0, 0, x0, x0, x0" :: "i"(RISCV_CUSTOM0));
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}
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// switch execution to single thread zero
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inline void vx_tmc_one() {
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__asm__ volatile (
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"li a0, 1\n\t" // Load immediate value 1 into a0 (x10) register
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".insn r %0, 0, 0, x0, a0, x0" :: "i"(RISCV_CUSTOM0) : "a0"
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);
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}
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// Set thread predicate
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inline void vx_pred(int condition, int thread_mask) {
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__asm__ volatile (".insn r %0, 5, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(condition), "r"(thread_mask));
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}
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// Set thread not predicate
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inline void vx_pred_n(int condition, int thread_mask) {
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__asm__ volatile (".insn r %0, 5, 0, x1, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(condition), "r"(thread_mask));
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}
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// Spawn warps
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typedef void (*vx_wspawn_pfn)();
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inline void vx_wspawn(int num_warps, vx_wspawn_pfn func_ptr) {
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__asm__ volatile (".insn r %0, 1, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(num_warps), "r"(func_ptr));
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}
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// Split on a predicate
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inline int vx_split(int predicate) {
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int ret;
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__asm__ volatile (".insn r %1, 2, 0, %0, %2, x0" : "=r"(ret) : "i"(RISCV_CUSTOM0), "r"(predicate));
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return ret;
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}
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// Split on a not predicate
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inline int vx_split_n(int predicate) {
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int ret;
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__asm__ volatile (".insn r %1, 2, 0, %0, %2, x1" : "=r"(ret) : "i"(RISCV_CUSTOM0), "r"(predicate));
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return ret;
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}
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// Join
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inline void vx_join(int stack_ptr) {
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__asm__ volatile (".insn r %0, 3, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(stack_ptr));
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}
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// Warp Barrier
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inline void vx_barrier(int barried_id, int num_warps) {
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__asm__ volatile (".insn r %0, 4, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(barried_id), "r"(num_warps));
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}
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// Return current thread identifier
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inline int vx_thread_id() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_ID));
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return ret;
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}
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// Return current warp identifier
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inline int vx_warp_id() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_ID));
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return ret;
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}
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// Return current core identifier
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inline int vx_core_id() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_CORE_ID));
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return ret;
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}
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// Return active threads mask
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inline int vx_active_threads() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_ACTIVE_THREADS));
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return ret;
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}
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// Return active warps mask
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inline int vx_active_warps() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_ACTIVE_WARPS));
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return ret;
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}
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// Return the number of threads per warp
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inline int vx_num_threads() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_THREADS));
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return ret;
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}
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// Return the number of warps per core
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inline int vx_num_warps() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_WARPS));
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return ret;
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}
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// Return the number of cores per cluster
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inline int vx_num_cores() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_CORES));
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return ret;
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}
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// Return the hart identifier (thread id accross the processor)
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inline int vx_hart_id() {
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int ret;
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__asm__ volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_MHARTID));
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return ret;
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}
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inline void vx_fence() {
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__asm__ volatile ("fence iorw, iorw");
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}
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//Matrix load
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inline void vx_matrix_load(unsigned dest, unsigned addr)
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{
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__asm__ volatile (".insn i 0x7b, 0, x0, %0(%1)" :: "i"(dest), "r"(addr));
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}
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//Matrix Store
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inline void vx_matrix_store(unsigned addr)
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{
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__asm__ volatile (".insn i 0x7b, 1, x0, 0(%0)" :: "r"(addr));
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}
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//Matrix Mul
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inline void vx_matrix_mul()
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{
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__asm__ volatile (".insn i 0x7b, 2, x0, 0(x0)");
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}
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#ifdef __cplusplus
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}
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#endif
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#endif // __VX_INTRINSICS_H__
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