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196 lines
8 KiB
Systemverilog
196 lines
8 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module rtlsim_shim import VX_gpu_pkg::*; #(
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parameter MEM_DATA_WIDTH = (`PLATFORM_MEMORY_DATA_SIZE * 8),
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parameter MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH - $clog2(`PLATFORM_MEMORY_NUM_BANKS),
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parameter MEM_NUM_BANKS = `PLATFORM_MEMORY_NUM_BANKS,
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parameter MEM_TAG_WIDTH = 64
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) (
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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// Memory request
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output wire mem_req_valid [MEM_NUM_BANKS],
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output wire mem_req_rw [MEM_NUM_BANKS],
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output wire [(MEM_DATA_WIDTH/8)-1:0] mem_req_byteen [MEM_NUM_BANKS],
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output wire [MEM_ADDR_WIDTH-1:0] mem_req_addr [MEM_NUM_BANKS],
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output wire [MEM_DATA_WIDTH-1:0] mem_req_data [MEM_NUM_BANKS],
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output wire [MEM_TAG_WIDTH-1:0] mem_req_tag [MEM_NUM_BANKS],
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input wire mem_req_ready [MEM_NUM_BANKS],
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// Memory response
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input wire mem_rsp_valid [MEM_NUM_BANKS],
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input wire [MEM_DATA_WIDTH-1:0] mem_rsp_data [MEM_NUM_BANKS],
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input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag [MEM_NUM_BANKS],
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output wire mem_rsp_ready [MEM_NUM_BANKS],
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// DCR write request
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input wire dcr_wr_valid,
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input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
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input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,
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// Status
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output wire busy
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);
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localparam DST_LDATAW = `CLOG2(MEM_DATA_WIDTH);
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localparam SRC_LDATAW = `CLOG2(`VX_MEM_DATA_WIDTH);
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localparam SUB_LDATAW = DST_LDATAW - SRC_LDATAW;
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localparam VX_MEM_TAG_A_WIDTH = `VX_MEM_TAG_WIDTH + `MAX(SUB_LDATAW, 0);
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localparam VX_MEM_ADDR_A_WIDTH = `VX_MEM_ADDR_WIDTH - SUB_LDATAW;
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wire vx_mem_req_valid [`VX_MEM_PORTS];
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wire vx_mem_req_rw [`VX_MEM_PORTS];
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wire [`VX_MEM_BYTEEN_WIDTH-1:0] vx_mem_req_byteen [`VX_MEM_PORTS];
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wire [`VX_MEM_ADDR_WIDTH-1:0] vx_mem_req_addr [`VX_MEM_PORTS];
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wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_req_data [`VX_MEM_PORTS];
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wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_req_tag [`VX_MEM_PORTS];
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wire vx_mem_req_ready [`VX_MEM_PORTS];
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wire vx_mem_rsp_valid [`VX_MEM_PORTS];
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wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_rsp_data [`VX_MEM_PORTS];
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wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag [`VX_MEM_PORTS];
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wire vx_mem_rsp_ready [`VX_MEM_PORTS];
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`SCOPE_IO_SWITCH (1);
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Vortex vortex (
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`SCOPE_IO_BIND (0)
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.clk (clk),
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.reset (reset),
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.mem_req_valid (vx_mem_req_valid),
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.mem_req_rw (vx_mem_req_rw),
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.mem_req_byteen (vx_mem_req_byteen),
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.mem_req_addr (vx_mem_req_addr),
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.mem_req_data (vx_mem_req_data),
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.mem_req_tag (vx_mem_req_tag),
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.mem_req_ready (vx_mem_req_ready),
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.mem_rsp_valid (vx_mem_rsp_valid),
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.mem_rsp_data (vx_mem_rsp_data),
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.mem_rsp_tag (vx_mem_rsp_tag),
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.mem_rsp_ready (vx_mem_rsp_ready),
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.dcr_wr_valid (dcr_wr_valid),
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.dcr_wr_addr (dcr_wr_addr),
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.dcr_wr_data (dcr_wr_data),
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.busy (busy)
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);
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wire mem_req_valid_a [`VX_MEM_PORTS];
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wire mem_req_rw_a [`VX_MEM_PORTS];
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wire [(MEM_DATA_WIDTH/8)-1:0] mem_req_byteen_a [`VX_MEM_PORTS];
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wire [VX_MEM_ADDR_A_WIDTH-1:0] mem_req_addr_a [`VX_MEM_PORTS];
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wire [MEM_DATA_WIDTH-1:0] mem_req_data_a [`VX_MEM_PORTS];
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wire [VX_MEM_TAG_A_WIDTH-1:0] mem_req_tag_a [`VX_MEM_PORTS];
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wire mem_req_ready_a [`VX_MEM_PORTS];
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wire mem_rsp_valid_a [`VX_MEM_PORTS];
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wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_a [`VX_MEM_PORTS];
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wire [VX_MEM_TAG_A_WIDTH-1:0] mem_rsp_tag_a [`VX_MEM_PORTS];
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wire mem_rsp_ready_a [`VX_MEM_PORTS];
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// Adjust memory data width to match AXI interface
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for (genvar i = 0; i < `VX_MEM_PORTS; i++) begin : g_mem_adapter
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VX_mem_data_adapter #(
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.SRC_DATA_WIDTH (`VX_MEM_DATA_WIDTH),
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.DST_DATA_WIDTH (MEM_DATA_WIDTH),
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.SRC_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH),
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.DST_ADDR_WIDTH (VX_MEM_ADDR_A_WIDTH),
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.SRC_TAG_WIDTH (`VX_MEM_TAG_WIDTH),
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.DST_TAG_WIDTH (VX_MEM_TAG_A_WIDTH),
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.REQ_OUT_BUF (0),
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.RSP_OUT_BUF (0)
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) mem_data_adapter (
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.clk (clk),
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.reset (reset),
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.mem_req_valid_in (vx_mem_req_valid[i]),
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.mem_req_addr_in (vx_mem_req_addr[i]),
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.mem_req_rw_in (vx_mem_req_rw[i]),
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.mem_req_byteen_in (vx_mem_req_byteen[i]),
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.mem_req_data_in (vx_mem_req_data[i]),
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.mem_req_tag_in (vx_mem_req_tag[i]),
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.mem_req_ready_in (vx_mem_req_ready[i]),
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.mem_rsp_valid_in (vx_mem_rsp_valid[i]),
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.mem_rsp_data_in (vx_mem_rsp_data[i]),
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.mem_rsp_tag_in (vx_mem_rsp_tag[i]),
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.mem_rsp_ready_in (vx_mem_rsp_ready[i]),
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.mem_req_valid_out (mem_req_valid_a[i]),
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.mem_req_addr_out (mem_req_addr_a[i]),
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.mem_req_rw_out (mem_req_rw_a[i]),
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.mem_req_byteen_out (mem_req_byteen_a[i]),
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.mem_req_data_out (mem_req_data_a[i]),
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.mem_req_tag_out (mem_req_tag_a[i]),
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.mem_req_ready_out (mem_req_ready_a[i]),
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.mem_rsp_valid_out (mem_rsp_valid_a[i]),
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.mem_rsp_data_out (mem_rsp_data_a[i]),
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.mem_rsp_tag_out (mem_rsp_tag_a[i]),
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.mem_rsp_ready_out (mem_rsp_ready_a[i])
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);
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end
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VX_mem_bank_adapter #(
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.DATA_WIDTH (MEM_DATA_WIDTH),
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.ADDR_WIDTH_IN (VX_MEM_ADDR_A_WIDTH),
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.ADDR_WIDTH_OUT (MEM_ADDR_WIDTH),
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.TAG_WIDTH_IN (VX_MEM_TAG_A_WIDTH),
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.TAG_WIDTH_OUT (MEM_TAG_WIDTH),
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.NUM_PORTS_IN (`VX_MEM_PORTS),
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.NUM_BANKS_OUT (MEM_NUM_BANKS),
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.INTERLEAVE (`PLATFORM_MEMORY_INTERLEAVE),
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.REQ_OUT_BUF ((`VX_MEM_PORTS > 1) ? 2 : 0),
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.RSP_OUT_BUF ((`VX_MEM_PORTS > 1 || MEM_NUM_BANKS > 1) ? 2 : 0)
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) mem_bank_adapter (
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.clk (clk),
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.reset (reset),
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.mem_req_valid_in (mem_req_valid_a),
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.mem_req_rw_in (mem_req_rw_a),
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.mem_req_byteen_in (mem_req_byteen_a),
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.mem_req_addr_in (mem_req_addr_a),
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.mem_req_data_in (mem_req_data_a),
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.mem_req_tag_in (mem_req_tag_a),
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.mem_req_ready_in (mem_req_ready_a),
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.mem_rsp_valid_in (mem_rsp_valid_a),
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.mem_rsp_data_in (mem_rsp_data_a),
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.mem_rsp_tag_in (mem_rsp_tag_a),
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.mem_rsp_ready_in (mem_rsp_ready_a),
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.mem_req_valid_out (mem_req_valid),
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.mem_req_rw_out (mem_req_rw),
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.mem_req_byteen_out (mem_req_byteen),
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.mem_req_addr_out (mem_req_addr),
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.mem_req_data_out (mem_req_data),
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.mem_req_tag_out (mem_req_tag),
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.mem_req_ready_out (mem_req_ready),
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.mem_rsp_valid_out (mem_rsp_valid),
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.mem_rsp_data_out (mem_rsp_data),
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.mem_rsp_tag_out (mem_rsp_tag),
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.mem_rsp_ready_out (mem_rsp_ready)
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);
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endmodule
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