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https://github.com/vortexgpgpu/vortex.git
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106 lines
3.4 KiB
C++
106 lines
3.4 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "cache_sim.h"
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namespace vortex {
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class CacheCluster : public SimObject<CacheCluster> {
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public:
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std::vector<std::vector<SimPort<MemReq>>> CoreReqPorts;
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std::vector<std::vector<SimPort<MemRsp>>> CoreRspPorts;
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SimPort<MemReq> MemReqPort;
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SimPort<MemRsp> MemRspPort;
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CacheCluster(const SimContext& ctx,
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const char* name,
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uint32_t num_inputs,
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uint32_t num_caches,
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uint32_t num_requests,
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const CacheSim::Config& cache_config)
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: SimObject(ctx, name)
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, CoreReqPorts(num_inputs, std::vector<SimPort<MemReq>>(num_requests, this))
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, CoreRspPorts(num_inputs, std::vector<SimPort<MemRsp>>(num_requests, this))
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, MemReqPort(this)
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, MemRspPort(this)
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, caches_(MAX(num_caches, 0x1)) {
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CacheSim::Config cache_config2(cache_config);
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if (0 == num_caches) {
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num_caches = 1;
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cache_config2.bypass = true;
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}
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char sname[100];
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std::vector<MemSwitch::Ptr> input_arbs(num_inputs);
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for (uint32_t j = 0; j < num_inputs; ++j) {
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snprintf(sname, 100, "%s-input-arb%d", name, j);
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input_arbs.at(j) = MemSwitch::Create(sname, ArbiterType::RoundRobin, num_requests, cache_config.num_inputs);
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for (uint32_t i = 0; i < num_requests; ++i) {
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this->CoreReqPorts.at(j).at(i).bind(&input_arbs.at(j)->ReqIn.at(i));
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input_arbs.at(j)->RspIn.at(i).bind(&this->CoreRspPorts.at(j).at(i));
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}
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}
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std::vector<MemSwitch::Ptr> mem_arbs(cache_config.num_inputs);
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for (uint32_t i = 0; i < cache_config.num_inputs; ++i) {
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snprintf(sname, 100, "%s-mem-arb%d", name, i);
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mem_arbs.at(i) = MemSwitch::Create(sname, ArbiterType::RoundRobin, num_inputs, num_caches);
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for (uint32_t j = 0; j < num_inputs; ++j) {
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input_arbs.at(j)->ReqOut.at(i).bind(&mem_arbs.at(i)->ReqIn.at(j));
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mem_arbs.at(i)->RspIn.at(j).bind(&input_arbs.at(j)->RspOut.at(i));
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}
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}
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snprintf(sname, 100, "%s-cache-arb", name);
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auto cache_arb = MemSwitch::Create(sname, ArbiterType::RoundRobin, num_caches, 1);
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for (uint32_t i = 0; i < num_caches; ++i) {
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snprintf(sname, 100, "%s-cache%d", name, i);
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caches_.at(i) = CacheSim::Create(sname, cache_config2);
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for (uint32_t j = 0; j < cache_config.num_inputs; ++j) {
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mem_arbs.at(j)->ReqOut.at(i).bind(&caches_.at(i)->CoreReqPorts.at(j));
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caches_.at(i)->CoreRspPorts.at(j).bind(&mem_arbs.at(j)->RspOut.at(i));
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}
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caches_.at(i)->MemReqPorts.at(0).bind(&cache_arb->ReqIn.at(i));
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cache_arb->RspIn.at(i).bind(&caches_.at(i)->MemRspPorts.at(0));
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}
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cache_arb->ReqOut.at(0).bind(&this->MemReqPort);
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this->MemRspPort.bind(&cache_arb->RspOut.at(0));
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}
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~CacheCluster() {}
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void reset() {}
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void tick() {}
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CacheSim::PerfStats perf_stats() const {
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CacheSim::PerfStats perf;
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for (auto cache : caches_) {
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perf += cache->perf_stats();
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}
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return perf;
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}
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private:
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std::vector<CacheSim::Ptr> caches_;
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};
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}
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