mirror of
https://github.com/vortexgpgpu/vortex.git
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163 lines
4.9 KiB
Systemverilog
163 lines
4.9 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_cluster import VX_gpu_pkg::*; #(
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parameter CLUSTER_ID = 0,
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parameter `STRING INSTANCE_ID = ""
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) (
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.slave mem_perf_if,
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`endif
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// DCRs
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VX_dcr_bus_if.slave dcr_bus_if,
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// Memory
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VX_mem_bus_if.master mem_bus_if,
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// Status
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output wire busy
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);
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`ifdef SCOPE
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localparam scope_socket = 0;
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`SCOPE_IO_SWITCH (`NUM_SOCKETS);
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`endif
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`ifdef PERF_ENABLE
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VX_mem_perf_if mem_perf_tmp_if();
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assign mem_perf_tmp_if.icache = 'x;
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assign mem_perf_tmp_if.dcache = 'x;
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assign mem_perf_tmp_if.l3cache = mem_perf_if.l3cache;
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assign mem_perf_tmp_if.lmem = 'x;
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assign mem_perf_tmp_if.mem = mem_perf_if.mem;
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`endif
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`ifdef GBAR_ENABLE
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VX_gbar_bus_if per_socket_gbar_bus_if[`NUM_SOCKETS]();
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VX_gbar_bus_if gbar_bus_if();
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`RESET_RELAY (gbar_reset, reset);
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VX_gbar_arb #(
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.NUM_REQS (`NUM_SOCKETS),
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.OUT_BUF ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
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) gbar_arb (
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.clk (clk),
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.reset (gbar_reset),
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.bus_in_if (per_socket_gbar_bus_if),
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.bus_out_if (gbar_bus_if)
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);
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VX_gbar_unit #(
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.INSTANCE_ID ($sformatf("gbar%0d", CLUSTER_ID))
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) gbar_unit (
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.clk (clk),
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.reset (gbar_reset),
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.gbar_bus_if (gbar_bus_if)
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);
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`endif
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VX_mem_bus_if #(
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
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) per_socket_mem_bus_if[`NUM_SOCKETS]();
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`RESET_RELAY (l2_reset, reset);
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VX_cache_wrap #(
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.INSTANCE_ID ($sformatf("%s-l2cache", INSTANCE_ID)),
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.CACHE_SIZE (`L2_CACHE_SIZE),
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.LINE_SIZE (`L2_LINE_SIZE),
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.NUM_BANKS (`L2_NUM_BANKS),
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.NUM_WAYS (`L2_NUM_WAYS),
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.WORD_SIZE (L2_WORD_SIZE),
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.NUM_REQS (L2_NUM_REQS),
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.CRSQ_SIZE (`L2_CRSQ_SIZE),
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.MSHR_SIZE (`L2_MSHR_SIZE),
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.MRSQ_SIZE (`L2_MRSQ_SIZE),
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.MREQ_SIZE (`L2_WRITEBACK ? `L2_MSHR_SIZE : `L2_MREQ_SIZE),
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.TAG_WIDTH (L2_TAG_WIDTH),
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.WRITE_ENABLE (1),
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.WRITEBACK (`L2_WRITEBACK),
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.DIRTY_BYTES (`L2_WRITEBACK),
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.UUID_WIDTH (`UUID_WIDTH),
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.CORE_OUT_BUF (2),
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.MEM_OUT_BUF (2),
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.NC_ENABLE (1),
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.PASSTHRU (!`L2_ENABLED)
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) l2cache (
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.clk (clk),
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.reset (l2_reset),
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`ifdef PERF_ENABLE
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.cache_perf (mem_perf_tmp_if.l2cache),
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`endif
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.core_bus_if (per_socket_mem_bus_if),
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.mem_bus_if (mem_bus_if)
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);
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///////////////////////////////////////////////////////////////////////////
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VX_dcr_bus_if socket_dcr_bus_tmp_if();
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assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END);
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assign socket_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
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assign socket_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;
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wire [`NUM_SOCKETS-1:0] per_socket_busy;
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VX_dcr_bus_if socket_dcr_bus_if();
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`BUFFER_DCR_BUS_IF (socket_dcr_bus_if, socket_dcr_bus_tmp_if, (`NUM_SOCKETS > 1));
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// Generate all sockets
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for (genvar socket_id = 0; socket_id < `NUM_SOCKETS; ++socket_id) begin : sockets
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`RESET_RELAY (socket_reset, reset);
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VX_socket #(
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.SOCKET_ID ((CLUSTER_ID * `NUM_SOCKETS) + socket_id),
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.INSTANCE_ID ($sformatf("%s-socket%0d", INSTANCE_ID, socket_id))
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) socket (
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`SCOPE_IO_BIND (scope_socket+socket_id)
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.clk (clk),
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.reset (socket_reset),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_tmp_if),
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`endif
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.dcr_bus_if (socket_dcr_bus_if),
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.mem_bus_if (per_socket_mem_bus_if[socket_id]),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (per_socket_gbar_bus_if[socket_id]),
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`endif
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.busy (per_socket_busy[socket_id])
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);
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end
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`BUFFER_EX(busy, (| per_socket_busy), 1'b1, (`NUM_SOCKETS > 1));
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endmodule
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