mirror of
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437 lines
16 KiB
Systemverilog
437 lines
16 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VX_DEFINE_VH
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`define VX_DEFINE_VH
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`include "VX_platform.vh"
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`include "VX_config.vh"
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`include "VX_types.vh"
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///////////////////////////////////////////////////////////////////////////////
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`define NW_BITS `CLOG2(`NUM_WARPS)
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`define NC_WIDTH `UP(`NC_BITS)
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`define NT_BITS `CLOG2(`NUM_THREADS)
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`define NW_WIDTH `UP(`NW_BITS)
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`define NC_BITS `CLOG2(`NUM_CORES)
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`define NT_WIDTH `UP(`NT_BITS)
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`define NB_BITS `CLOG2(`NUM_BARRIERS)
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`define NB_WIDTH `UP(`NB_BITS)
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`define NUM_IREGS 32
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`define NRI_BITS `CLOG2(`NUM_IREGS)
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`ifdef EXT_F_ENABLE
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`define NUM_REGS (2 * `NUM_IREGS)
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`else
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`define NUM_REGS `NUM_IREGS
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`endif
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`define NR_BITS `CLOG2(`NUM_REGS)
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`define DV_STACK_SIZE `UP(`NUM_THREADS-1)
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`define DV_STACK_SIZEW `UP(`CLOG2(`DV_STACK_SIZE))
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`define PERF_CTR_BITS 44
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`ifndef NDEBUG
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`define UUID_WIDTH 44
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`else
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`define UUID_WIDTH 1
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`endif
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`define PC_BITS (`XLEN-1)
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`define OFFSET_BITS 12
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`define IMM_BITS `XLEN
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`define NUM_SOCKETS `UP(`NUM_CORES / `SOCKET_SIZE)
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///////////////////////////////////////////////////////////////////////////////
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`define EX_ALU 0
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`define EX_LSU 1
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`define EX_SFU 2
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`define EX_FPU (`EX_SFU + `EXT_F_ENABLED)
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`define NUM_EX_UNITS (3 + `EXT_F_ENABLED)
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`define EX_BITS `CLOG2(`NUM_EX_UNITS)
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`define EX_WIDTH `UP(`EX_BITS)
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`define SFU_CSRS 0
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`define SFU_WCTL 1
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`define NUM_SFU_UNITS (2)
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`define SFU_BITS `CLOG2(`NUM_SFU_UNITS)
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`define SFU_WIDTH `UP(`SFU_BITS)
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///////////////////////////////////////////////////////////////////////////////
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`define INST_LUI 7'b0110111
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`define INST_AUIPC 7'b0010111
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`define INST_JAL 7'b1101111
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`define INST_JALR 7'b1100111
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`define INST_B 7'b1100011 // branch instructions
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`define INST_L 7'b0000011 // load instructions
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`define INST_S 7'b0100011 // store instructions
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`define INST_I 7'b0010011 // immediate instructions
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`define INST_R 7'b0110011 // register instructions
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`define INST_FENCE 7'b0001111 // Fence instructions
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`define INST_SYS 7'b1110011 // system instructions
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// RV64I instruction specific opcodes (for any W instruction)
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`define INST_I_W 7'b0011011 // W type immediate instructions
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`define INST_R_W 7'b0111011 // W type register instructions
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`define INST_FL 7'b0000111 // float load instruction
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`define INST_FS 7'b0100111 // float store instruction
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`define INST_FMADD 7'b1000011
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`define INST_FMSUB 7'b1000111
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`define INST_FNMSUB 7'b1001011
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`define INST_FNMADD 7'b1001111
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`define INST_FCI 7'b1010011 // float common instructions
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// Custom extension opcodes
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`define INST_EXT1 7'b0001011 // 0x0B
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`define INST_EXT2 7'b0101011 // 0x2B
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`define INST_EXT3 7'b1011011 // 0x5B
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`define INST_EXT4 7'b1111011 // 0x7B
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// Opcode extensions
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`define INST_R_F7_MUL 7'b0000001
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`define INST_R_F7_ZICOND 7'b0000111
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///////////////////////////////////////////////////////////////////////////////
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`define INST_FRM_RNE 3'b000 // round to nearest even
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`define INST_FRM_RTZ 3'b001 // round to zero
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`define INST_FRM_RDN 3'b010 // round to -inf
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`define INST_FRM_RUP 3'b011 // round to +inf
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`define INST_FRM_RMM 3'b100 // round to nearest max magnitude
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`define INST_FRM_DYN 3'b111 // dynamic mode
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`define INST_FRM_BITS 3
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///////////////////////////////////////////////////////////////////////////////
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`define INST_OP_BITS 4
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`define INST_ARGS_BITS $bits(op_args_t)
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`define INST_FMT_BITS 2
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///////////////////////////////////////////////////////////////////////////////
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`define INST_ALU_ADD 4'b0000
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//`define INST_ALU_UNUSED 4'b0001
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`define INST_ALU_LUI 4'b0010
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`define INST_ALU_AUIPC 4'b0011
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`define INST_ALU_SLTU 4'b0100
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`define INST_ALU_SLT 4'b0101
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//`define INST_ALU_UNUSED 4'b0110
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`define INST_ALU_SUB 4'b0111
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`define INST_ALU_SRL 4'b1000
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`define INST_ALU_SRA 4'b1001
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`define INST_ALU_CZEQ 4'b1010
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`define INST_ALU_CZNE 4'b1011
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`define INST_ALU_AND 4'b1100
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`define INST_ALU_OR 4'b1101
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`define INST_ALU_XOR 4'b1110
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`define INST_ALU_SLL 4'b1111
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`define ALU_TYPE_BITS 2
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`define ALU_TYPE_ARITH 0
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`define ALU_TYPE_BRANCH 1
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`define ALU_TYPE_MULDIV 2
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`define ALU_TYPE_OTHER 3
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`define INST_ALU_BITS 4
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`define INST_ALU_CLASS(op) op[3:2]
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`define INST_ALU_SIGNED(op) op[0]
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`define INST_ALU_IS_SUB(op) op[1]
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`define INST_ALU_IS_CZERO(op) (op[3:1] == 3'b101)
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`define INST_BR_EQ 4'b0000
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`define INST_BR_NE 4'b0010
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`define INST_BR_LTU 4'b0100
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`define INST_BR_GEU 4'b0110
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`define INST_BR_LT 4'b0101
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`define INST_BR_GE 4'b0111
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`define INST_BR_JAL 4'b1000
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`define INST_BR_JALR 4'b1001
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`define INST_BR_ECALL 4'b1010
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`define INST_BR_EBREAK 4'b1011
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`define INST_BR_URET 4'b1100
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`define INST_BR_SRET 4'b1101
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`define INST_BR_MRET 4'b1110
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`define INST_BR_OTHER 4'b1111
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`define INST_BR_BITS 4
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`define INST_BR_CLASS(op) {1'b0, ~op[3]}
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`define INST_BR_IS_NEG(op) op[1]
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`define INST_BR_IS_LESS(op) op[2]
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`define INST_BR_IS_STATIC(op) op[3]
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`define INST_M_MUL 3'b000
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`define INST_M_MULHU 3'b001
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`define INST_M_MULH 3'b010
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`define INST_M_MULHSU 3'b011
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`define INST_M_DIV 3'b100
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`define INST_M_DIVU 3'b101
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`define INST_M_REM 3'b110
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`define INST_M_REMU 3'b111
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`define INST_M_BITS 3
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`define INST_M_SIGNED(op) (~op[0])
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`define INST_M_IS_MULX(op) (~op[2])
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`define INST_M_IS_MULH(op) (op[1:0] != 0)
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`define INST_M_SIGNED_A(op) (op[1:0] != 1)
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`define INST_M_IS_REM(op) op[1]
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`define INST_FMT_B 3'b000
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`define INST_FMT_H 3'b001
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`define INST_FMT_W 3'b010
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`define INST_FMT_D 3'b011
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`define INST_FMT_BU 3'b100
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`define INST_FMT_HU 3'b101
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`define INST_FMT_WU 3'b110
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`define INST_LSU_LB 4'b0000
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`define INST_LSU_LH 4'b0001
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`define INST_LSU_LW 4'b0010
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`define INST_LSU_LD 4'b0011 // new for RV64I LD
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`define INST_LSU_LBU 4'b0100
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`define INST_LSU_LHU 4'b0101
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`define INST_LSU_LWU 4'b0110 // new for RV64I LWU
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`define INST_LSU_SB 4'b1000
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`define INST_LSU_SH 4'b1001
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`define INST_LSU_SW 4'b1010
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`define INST_LSU_SD 4'b1011 // new for RV64I SD
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`define INST_LSU_FENCE 4'b1111
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`define INST_LSU_BITS 4
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`define INST_LSU_FMT(op) op[2:0]
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`define INST_LSU_WSIZE(op) op[1:0]
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`define INST_LSU_IS_FENCE(op) (op[3:2] == 3)
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`define INST_FENCE_BITS 1
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`define INST_FENCE_D 1'h0
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`define INST_FENCE_I 1'h1
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`define INST_FPU_ADD 4'b0000
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`define INST_FPU_SUB 4'b0001
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`define INST_FPU_MUL 4'b0010
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`define INST_FPU_DIV 4'b0011
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`define INST_FPU_SQRT 4'b0100
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`define INST_FPU_CMP 4'b0101 // frm: LE=0, LT=1, EQ=2
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`define INST_FPU_F2F 4'b0110
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`define INST_FPU_MISC 4'b0111 // frm: SGNJ=0, SGNJN=1, SGNJX=2, CLASS=3, MVXW=4, MVWX=5, FMIN=6, FMAX=7
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`define INST_FPU_F2I 4'b1000
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`define INST_FPU_F2U 4'b1001
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`define INST_FPU_I2F 4'b1010
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`define INST_FPU_U2F 4'b1011
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`define INST_FPU_MADD 4'b1100
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`define INST_FPU_MSUB 4'b1101
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`define INST_FPU_NMSUB 4'b1110
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`define INST_FPU_NMADD 4'b1111
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`define INST_FPU_BITS 4
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`define INST_FPU_IS_CLASS(op, frm) (op == `INST_FPU_MISC && frm == 3)
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`define INST_FPU_IS_MVXW(op, frm) (op == `INST_FPU_MISC && frm == 4)
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`define INST_SFU_TMC 4'h0
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`define INST_SFU_WSPAWN 4'h1
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`define INST_SFU_SPLIT 4'h2
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`define INST_SFU_JOIN 4'h3
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`define INST_SFU_BAR 4'h4
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`define INST_SFU_PRED 4'h5
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`define INST_SFU_CSRRW 4'h6
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`define INST_SFU_CSRRS 4'h7
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`define INST_SFU_CSRRC 4'h8
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`define INST_SFU_BITS 4
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`define INST_SFU_CSR(f3) (4'h6 + 4'(f3) - 4'h1)
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`define INST_SFU_IS_WCTL(op) (op <= 5)
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`define INST_SFU_IS_CSR(op) (op >= 6 && op <= 8)
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///////////////////////////////////////////////////////////////////////////////
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`define ARB_SEL_BITS(I, O) ((I > O) ? `CLOG2(`CDIV(I, O)) : 0)
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///////////////////////////////////////////////////////////////////////////////
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`define CACHE_MEM_TAG_WIDTH(mshr_size, num_banks) \
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(`CLOG2(mshr_size) + `CLOG2(num_banks))
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`define CACHE_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width) \
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(`CLOG2(num_reqs) + `CLOG2(line_size / word_size) + tag_width)
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`define CACHE_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, line_size, word_size, tag_width) \
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(`MAX(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks), `CACHE_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, tag_width)) + 1)
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///////////////////////////////////////////////////////////////////////////////
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`define CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches) \
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(tag_width + `ARB_SEL_BITS(num_inputs, `UP(num_caches)))
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`define CACHE_CLUSTER_MEM_ARB_TAG(tag_width, num_caches) \
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(tag_width + `ARB_SEL_BITS(`UP(num_caches), 1))
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`define CACHE_CLUSTER_MEM_TAG_WIDTH(mshr_size, num_banks, num_caches) \
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`CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks), num_caches)
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`define CACHE_CLUSTER_BYPASS_MEM_TAG_WIDTH(num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \
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`CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_BYPASS_TAG_WIDTH(num_reqs, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches)), num_caches)
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`define CACHE_CLUSTER_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, line_size, word_size, tag_width, num_inputs, num_caches) \
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`CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches)), num_caches)
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///////////////////////////////////////////////////////////////////////////////
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`ifdef ICACHE_ENABLE
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`define L1_ENABLE
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`endif
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`ifdef DCACHE_ENABLE
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`define L1_ENABLE
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`endif
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`define ADDR_TYPE_FLUSH 0
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`define ADDR_TYPE_IO 1
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`define ADDR_TYPE_LOCAL 2 // shoud be last since optional
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`define ADDR_TYPE_WIDTH (`ADDR_TYPE_LOCAL + `LMEM_ENABLED)
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`define VX_MEM_BYTEEN_WIDTH `L3_LINE_SIZE
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`define VX_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH - `CLOG2(`L3_LINE_SIZE))
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`define VX_MEM_DATA_WIDTH (`L3_LINE_SIZE * 8)
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`define VX_MEM_TAG_WIDTH L3_MEM_TAG_WIDTH
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`define VX_DCR_ADDR_WIDTH `VX_DCR_ADDR_BITS
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`define VX_DCR_DATA_WIDTH 32
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`define TO_FULL_ADDR(x) {x, (`MEM_ADDR_WIDTH-$bits(x))'(0)}
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///////////////////////////////////////////////////////////////////////////////
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`define BUFFER_EX(dst, src, ena, latency) \
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VX_pipe_register #( \
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.DATAW ($bits(dst)), \
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.RESETW ($bits(dst)), \
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.DEPTH (latency) \
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) __``dst``__ ( \
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.clk (clk), \
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.reset (reset), \
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.enable (ena), \
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.data_in (src), \
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.data_out (dst) \
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)
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`define BUFFER(dst, src) `BUFFER_EX(dst, src, 1'b1, 1)
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`define POP_COUNT_EX(out, in, model) \
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VX_popcount #( \
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.N ($bits(in)), \
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.MODEL (model) \
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) __``out``__ ( \
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.data_in (in), \
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.data_out (out) \
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)
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`define POP_COUNT(out, in) `POP_COUNT_EX(out, in, 1)
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`define ASSIGN_VX_IF(dst, src) \
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assign dst.valid = src.valid; \
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assign dst.data = src.data; \
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assign src.ready = dst.ready
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`define ASSIGN_VX_MEM_BUS_IF(dst, src) \
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assign dst.req_valid = src.req_valid; \
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assign dst.req_data = src.req_data; \
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assign src.req_ready = dst.req_ready; \
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assign src.rsp_valid = dst.rsp_valid; \
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assign src.rsp_data = dst.rsp_data; \
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assign dst.rsp_ready = src.rsp_ready
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`define ASSIGN_VX_MEM_BUS_IF_X(dst, src, TD, TS) \
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assign dst.req_valid = src.req_valid; \
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assign dst.req_data.rw = src.req_data.rw; \
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assign dst.req_data.byteen = src.req_data.byteen; \
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assign dst.req_data.addr = src.req_data.addr; \
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assign dst.req_data.atype = src.req_data.atype; \
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assign dst.req_data.data = src.req_data.data; \
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if (TD != TS) \
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assign dst.req_data.tag = {src.req_data.tag, {(TD-TS){1'b0}}}; \
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else \
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assign dst.req_data.tag = src.req_data.tag; \
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assign src.req_ready = dst.req_ready; \
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assign src.rsp_valid = dst.rsp_valid; \
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assign src.rsp_data.data = dst.rsp_data.data; \
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assign src.rsp_data.tag = dst.rsp_data.tag[TD-1 -: TS]; \
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assign dst.rsp_ready = src.rsp_ready
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`define ASSIGN_VX_LSU_MEM_IF(dst, src) \
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assign dst.req_valid = src.req_valid; \
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assign dst.req_data = src.req_data; \
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assign src.req_ready = dst.req_ready; \
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assign src.rsp_valid = dst.rsp_valid; \
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assign src.rsp_data = dst.rsp_data; \
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assign dst.rsp_ready = src.rsp_ready
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`define BUFFER_DCR_BUS_IF(dst, src, enable) \
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if (enable) begin \
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reg [(1 + `VX_DCR_ADDR_WIDTH + `VX_DCR_DATA_WIDTH)-1:0] __dst; \
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always @(posedge clk) begin \
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__dst <= {src.write_valid, src.write_addr, src.write_data}; \
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end \
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assign {dst.write_valid, dst.write_addr, dst.write_data} = __dst; \
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end else begin \
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assign {dst.write_valid, dst.write_addr, dst.write_data} = {src.write_valid, src.write_addr, src.write_data}; \
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end
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`define PERF_COUNTER_ADD(dst, src, field, width, count, reg_enable) \
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if (count > 1) begin \
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wire [count-1:0][width-1:0] __reduce_add_i_field; \
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wire [width-1:0] __reduce_add_o_field; \
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for (genvar __i = 0; __i < count; ++__i) begin \
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assign __reduce_add_i_field[__i] = src[__i].``field; \
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end \
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VX_reduce #(.DATAW_IN(width), .N(count), .OP("+")) __reduce_add_field ( \
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__reduce_add_i_field, \
|
|
__reduce_add_o_field \
|
|
); \
|
|
if (reg_enable) begin \
|
|
reg [width-1:0] __reduce_add_r_field; \
|
|
always @(posedge clk) begin \
|
|
if (reset) begin \
|
|
__reduce_add_r_field <= '0; \
|
|
end else begin \
|
|
__reduce_add_r_field <= __reduce_add_o_field; \
|
|
end \
|
|
end \
|
|
assign dst.``field = __reduce_add_r_field; \
|
|
end else begin \
|
|
assign dst.``field = __reduce_add_o_field; \
|
|
end \
|
|
end else begin \
|
|
assign dst.``field = src[0].``field; \
|
|
end
|
|
|
|
`define ASSIGN_BLOCKED_WID(dst, src, block_idx, block_size) \
|
|
if (block_size != 1) begin \
|
|
if (block_size != `NUM_WARPS) begin \
|
|
assign dst = {src[`NW_WIDTH-1:`CLOG2(block_size)], `CLOG2(block_size)'(block_idx)}; \
|
|
end else begin \
|
|
assign dst = `NW_WIDTH'(block_idx); \
|
|
end \
|
|
end else begin \
|
|
assign dst = src; \
|
|
end
|
|
|
|
`endif // VX_DEFINE_VH
|