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https://github.com/vortexgpgpu/vortex.git
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94 lines
No EOL
2.8 KiB
Text
94 lines
No EOL
2.8 KiB
Text
## To configure quartus and opae. Run this after logging in.
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source /export/fpga/bin/setup-fpga-env fpga-pac-a10
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# Configure a Quartus build area
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afu_synth_setup -s sources.txt build_fpga
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# Run Quartus in the vLab batch queue
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cd build_fpga && qsub-synth
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# check last 10 lines in build log for possible errors
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tail -n 10 ./build_arria10_fpga_1c/build.log
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# Check if the job is submitted to the queue and running. Status should be R
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qstat | grep <user>
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# Constantly monitoring the job submitted to the queue. Stop this using Ctrl+C
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watch ‘qstat | grep <user>’
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#
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## Executing on FPGA
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#
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# From the build_fpga directory acquire a fpga node
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qsub-fpga
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# Go to the directory whree qsub-synth was run above
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cd $PBS_O_WORKDIR
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# Load the image onto an FPGA
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fpgaconf <build>/synth/vortex_afu.gbs
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# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
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fpgaconf --bus 0xaf <build>/synth/vortex_afu.gbs
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# get portid
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fpgainfo port
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# Running the Test case
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cd /driver/tests/basic
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make run-fpga
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#
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## ASE build instructions
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#
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source /export/fpga/bin/setup-fpga-env fpga-pac-a10
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# Acquire a sever node for running ASE simulations
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qsub-sim
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# build ASE runtime
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TARGET=asesim make -C runtime/opae
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# build ASE hw image
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PREFIX=build_base CONFIGS="-DEXT_F_DISABLE -DL1_DISABLE -DSM_DISABLE -DNUM_WARPS=2 -DNUM_THREADS=2" TARGET=asesim make
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# ASE test runs
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./run_ase.sh build_base_arria10_asesim_1c ../../../../tests/regression/basic/basic -n1 -t0
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./run_ase.sh build_base_arria10_asesim_1c ../../../../tests/regression/basic/basic -n1 -t1
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./run_ase.sh build_base_arria10_asesim_1c ../../../../tests/regression/basic/basic -n16
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./run_ase.sh build_base_arria10_asesim_1c ../../../../tests/regression/demo/demo -n16
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./run_ase.sh build_base_arria10_asesim_1c ../../../../tests/regression/dogfood/dogfood -n16
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./run_ase.sh build_base_arria10_asesim_1c ../../../../tests/opencl/vecadd/vecadd
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./run_ase.sh build_base_arria10_asesim_1c ../../../../tests/opencl/sgemm/sgemm -n4
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# modify "vsim_run.tcl" to dump VCD trace
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vcd file trace.vcd
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vcd add -r /*/afu/*
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run -all
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# compress FPGA output files
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tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt -o -iname \*.txt -o -iname \*summary -o -iname \*.log \)`
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# compress log trace
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tar -zcvf run.log.tar.gz run.log
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tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
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tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/synth/work/run.log build_arria10_ase_1c/work/trace.vcd
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# decompress log trace
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tar -zxvf vortex.vcd.tar.gz
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tar -xvf vortex.vcd.tar.bz2
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# building FPGA images
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make all
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# running benchmarks on FPGA
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fpgaconf --bus 0xaf <build>/synth/vortex_afu.gbs
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TARGET=fpga ./ci/blackbox.sh --driver=opae --app=sgemm
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# quick off synthesis
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make core
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# generate reports
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./report_timing.sh <project_dir> <project_name>
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./report_area.sh <project_dir> <project_name> |