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132 lines
4 KiB
Systemverilog
132 lines
4 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_fifo_queue #(
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parameter DATAW = 32,
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parameter DEPTH = 32,
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parameter ALM_FULL = (DEPTH - 1),
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parameter ALM_EMPTY = 1,
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parameter OUT_REG = 0,
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parameter LUTRAM = 0,
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parameter SIZEW = `CLOG2(DEPTH+1)
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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output wire empty,
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output wire alm_empty,
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output wire full,
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output wire alm_full,
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output wire [SIZEW-1:0] size
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);
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`STATIC_ASSERT(ALM_FULL > 0, ("alm_full must be greater than 0!"))
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`STATIC_ASSERT(ALM_FULL < DEPTH, ("alm_full must be smaller than size!"))
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`STATIC_ASSERT(ALM_EMPTY > 0, ("alm_empty must be greater than 0!"))
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`STATIC_ASSERT(ALM_EMPTY < DEPTH, ("alm_empty must be smaller than size!"))
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`STATIC_ASSERT(`IS_POW2(DEPTH), ("depth must be a power of 2!"))
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VX_pending_size #(
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.SIZE (DEPTH),
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.ALM_EMPTY (ALM_EMPTY),
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.ALM_FULL (ALM_FULL)
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) pending_size (
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.clk (clk),
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.reset (reset),
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.incr (push),
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.decr (pop),
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.empty (empty),
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.full (full),
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.alm_empty(alm_empty),
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.alm_full(alm_full),
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.size (size)
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);
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if (DEPTH == 1) begin : g_depth_1
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`UNUSED_PARAM (OUT_REG)
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`UNUSED_PARAM (LUTRAM)
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reg [DATAW-1:0] head_r;
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always @(posedge clk) begin
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if (push) begin
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head_r <= data_in;
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end
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end
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assign data_out = head_r;
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end else begin : g_depth_n
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localparam ADDRW = `CLOG2(DEPTH);
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wire [DATAW-1:0] data_out_w;
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reg [ADDRW-1:0] rd_ptr_r;
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reg [ADDRW-1:0] wr_ptr_r;
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always @(posedge clk) begin
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if (reset) begin
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wr_ptr_r <= '0;
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rd_ptr_r <= (OUT_REG != 0) ? 1 : 0;
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end else begin
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wr_ptr_r <= wr_ptr_r + ADDRW'(push);
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rd_ptr_r <= rd_ptr_r + ADDRW'(pop);
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end
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end
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wire going_empty = (ALM_EMPTY == 1) ? alm_empty : (size[ADDRW-1:0] == ADDRW'(1));
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wire bypass = push && (empty || (going_empty && pop));
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (DEPTH),
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.LUTRAM (LUTRAM),
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.RDW_MODE ("W")
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) dp_ram (
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.clk (clk),
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.reset (reset),
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.read (~bypass),
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.write (push),
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.wren (1'b1),
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.raddr (rd_ptr_r),
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.waddr (wr_ptr_r),
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.wdata (data_in),
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.rdata (data_out_w)
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);
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if (OUT_REG != 0) begin : g_out_reg
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reg [DATAW-1:0] data_out_r;
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always @(posedge clk) begin
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if (bypass) begin
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data_out_r <= data_in;
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end else if (pop) begin
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data_out_r <= data_out_w;
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end
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end
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assign data_out = data_out_r;
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end else begin : g_no_out_reg
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assign data_out = data_out_w;
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end
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end
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`RUNTIME_ASSERT(~(push && ~pop) || ~full, ("%t: runtime error: incrementing full queue", $time))
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`RUNTIME_ASSERT(~(pop && ~push) || ~empty, ("%t: runtime error: decrementing empty queue", $time))
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endmodule
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`TRACING_ON
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