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https://github.com/vortexgpgpu/vortex.git
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259 lines
10 KiB
Systemverilog
259 lines
10 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_mem_adapter #(
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parameter SRC_DATA_WIDTH = 1,
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parameter SRC_ADDR_WIDTH = 1,
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parameter DST_DATA_WIDTH = 1,
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parameter DST_ADDR_WIDTH = 1,
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parameter SRC_TAG_WIDTH = 1,
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parameter DST_TAG_WIDTH = 1,
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parameter REQ_OUT_BUF = 0,
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parameter RSP_OUT_BUF = 0
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) (
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input wire clk,
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input wire reset,
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input wire mem_req_valid_in,
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input wire [SRC_ADDR_WIDTH-1:0] mem_req_addr_in,
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input wire mem_req_rw_in,
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input wire [SRC_DATA_WIDTH/8-1:0] mem_req_byteen_in,
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input wire [SRC_DATA_WIDTH-1:0] mem_req_data_in,
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input wire [SRC_TAG_WIDTH-1:0] mem_req_tag_in,
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output wire mem_req_ready_in,
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output wire mem_rsp_valid_in,
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output wire [SRC_DATA_WIDTH-1:0] mem_rsp_data_in,
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output wire [SRC_TAG_WIDTH-1:0] mem_rsp_tag_in,
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input wire mem_rsp_ready_in,
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output wire mem_req_valid_out,
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output wire [DST_ADDR_WIDTH-1:0] mem_req_addr_out,
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output wire mem_req_rw_out,
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output wire [DST_DATA_WIDTH/8-1:0] mem_req_byteen_out,
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output wire [DST_DATA_WIDTH-1:0] mem_req_data_out,
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output wire [DST_TAG_WIDTH-1:0] mem_req_tag_out,
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input wire mem_req_ready_out,
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input wire mem_rsp_valid_out,
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input wire [DST_DATA_WIDTH-1:0] mem_rsp_data_out,
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input wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_out,
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output wire mem_rsp_ready_out
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);
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localparam DST_DATA_SIZE = (DST_DATA_WIDTH / 8);
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localparam DST_LDATAW = `CLOG2(DST_DATA_WIDTH);
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localparam SRC_LDATAW = `CLOG2(SRC_DATA_WIDTH);
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localparam D = `ABS(DST_LDATAW - SRC_LDATAW);
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localparam P = 2**D;
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localparam EXPECTED_TAG_WIDTH = SRC_TAG_WIDTH + ((DST_LDATAW > SRC_LDATAW) ? D : 0);
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`STATIC_ASSERT(DST_TAG_WIDTH >= EXPECTED_TAG_WIDTH, ("invalid DST_TAG_WIDTH parameter, current=%0d, expected=%0d", DST_TAG_WIDTH, EXPECTED_TAG_WIDTH))
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wire mem_req_valid_out_w;
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wire [DST_ADDR_WIDTH-1:0] mem_req_addr_out_w;
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wire mem_req_rw_out_w;
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wire [DST_DATA_WIDTH/8-1:0] mem_req_byteen_out_w;
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wire [DST_DATA_WIDTH-1:0] mem_req_data_out_w;
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wire [DST_TAG_WIDTH-1:0] mem_req_tag_out_w;
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wire mem_req_ready_out_w;
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wire mem_rsp_valid_in_w;
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wire [SRC_DATA_WIDTH-1:0] mem_rsp_data_in_w;
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wire [SRC_TAG_WIDTH-1:0] mem_rsp_tag_in_w;
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wire mem_rsp_ready_in_w;
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`UNUSED_VAR (mem_req_tag_in)
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`UNUSED_VAR (mem_rsp_tag_out)
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if (DST_LDATAW > SRC_LDATAW) begin : g_wider_dst_data
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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wire [D-1:0] req_idx = mem_req_addr_in[D-1:0];
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wire [D-1:0] rsp_idx = mem_rsp_tag_out[D-1:0];
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wire [SRC_ADDR_WIDTH-D-1:0] mem_req_addr_in_qual = mem_req_addr_in[SRC_ADDR_WIDTH-1:D];
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wire [P-1:0][SRC_DATA_WIDTH-1:0] mem_rsp_data_out_w = mem_rsp_data_out;
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if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH - D)) begin : g_mem_req_addr_out_w_src
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`UNUSED_VAR (mem_req_addr_in_qual)
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assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0];
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end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH - D)) begin : g_mem_req_addr_out_w_dst
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assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual);
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end else begin : g_mem_req_addr_out_w
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assign mem_req_addr_out_w = mem_req_addr_in_qual;
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end
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VX_demux #(
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.N (D),
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.M (SRC_DATA_WIDTH/8)
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) req_be_demux (
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.sel_in (req_idx),
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.data_in (mem_req_byteen_in),
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.data_out (mem_req_byteen_out_w)
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);
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VX_demux #(
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.N (D),
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.M (SRC_DATA_WIDTH)
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) req_data_demux (
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.sel_in (req_idx),
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.data_in (mem_req_data_in),
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.data_out (mem_req_data_out_w)
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);
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assign mem_req_valid_out_w = mem_req_valid_in;
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assign mem_req_rw_out_w = mem_req_rw_in;
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assign mem_req_tag_out_w = DST_TAG_WIDTH'({mem_req_tag_in, req_idx});
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assign mem_req_ready_in = mem_req_ready_out_w;
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assign mem_rsp_valid_in_w = mem_rsp_valid_out;
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assign mem_rsp_data_in_w = mem_rsp_data_out_w[rsp_idx];
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assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out[DST_TAG_WIDTH-1:D]);
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assign mem_rsp_ready_out = mem_rsp_ready_in_w;
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end else if (DST_LDATAW < SRC_LDATAW) begin : g_wider_src_data
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reg [D-1:0] req_ctr, rsp_ctr;
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reg [P-1:0][DST_DATA_WIDTH-1:0] mem_rsp_data_out_r, mem_rsp_data_out_n;
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wire mem_req_out_fire = mem_req_valid_out && mem_req_ready_out;
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wire mem_rsp_in_fire = mem_rsp_valid_out && mem_rsp_ready_out;
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wire [P-1:0][DST_DATA_WIDTH-1:0] mem_req_data_in_w = mem_req_data_in;
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wire [P-1:0][DST_DATA_SIZE-1:0] mem_req_byteen_in_w = mem_req_byteen_in;
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always @(*) begin
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mem_rsp_data_out_n = mem_rsp_data_out_r;
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if (mem_rsp_in_fire) begin
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mem_rsp_data_out_n[rsp_ctr] = mem_rsp_data_out;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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req_ctr <= '0;
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rsp_ctr <= '0;
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end else begin
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if (mem_req_out_fire) begin
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req_ctr <= req_ctr + 1;
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end
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if (mem_rsp_in_fire) begin
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rsp_ctr <= rsp_ctr + 1;
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end
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end
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mem_rsp_data_out_r <= mem_rsp_data_out_n;
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end
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reg [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_r;
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wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_x;
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always @(posedge clk) begin
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if (mem_rsp_in_fire) begin
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mem_rsp_tag_in_r <= mem_rsp_tag_out;
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end
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end
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assign mem_rsp_tag_in_x = (rsp_ctr != 0) ? mem_rsp_tag_in_r : mem_rsp_tag_out;
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`RUNTIME_ASSERT(!mem_rsp_in_fire || (mem_rsp_tag_in_x == mem_rsp_tag_out),
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("%t: *** out-of-order memory reponse! cur=0x%0h, expected=0x%0h", $time, mem_rsp_tag_in_x, mem_rsp_tag_out))
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wire [SRC_ADDR_WIDTH+D-1:0] mem_req_addr_in_qual = {mem_req_addr_in, req_ctr};
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if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH + D)) begin : g_mem_req_addr_out_w_src
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`UNUSED_VAR (mem_req_addr_in_qual)
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assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0];
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end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH + D)) begin : g_mem_req_addr_out_w_dst
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assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual);
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end else begin : g_mem_req_addr_out_w
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assign mem_req_addr_out_w = mem_req_addr_in_qual;
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end
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assign mem_req_valid_out_w = mem_req_valid_in;
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assign mem_req_rw_out_w = mem_req_rw_in;
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assign mem_req_byteen_out_w = mem_req_byteen_in_w[req_ctr];
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assign mem_req_data_out_w = mem_req_data_in_w[req_ctr];
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assign mem_req_tag_out_w = DST_TAG_WIDTH'(mem_req_tag_in);
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assign mem_req_ready_in = mem_req_ready_out_w && (req_ctr == (P-1));
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assign mem_rsp_valid_in_w = mem_rsp_valid_out && (rsp_ctr == (P-1));
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assign mem_rsp_data_in_w = mem_rsp_data_out_n;
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assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out);
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assign mem_rsp_ready_out = mem_rsp_ready_in_w;
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end else begin : g_passthru
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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if (DST_ADDR_WIDTH < SRC_ADDR_WIDTH) begin : g_mem_req_addr_out_w_src
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`UNUSED_VAR (mem_req_addr_in)
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assign mem_req_addr_out_w = mem_req_addr_in[DST_ADDR_WIDTH-1:0];
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end else if (DST_ADDR_WIDTH > SRC_ADDR_WIDTH) begin : g_mem_req_addr_out_w_dst
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assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in);
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end else begin : g_mem_req_addr_out_w
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assign mem_req_addr_out_w = mem_req_addr_in;
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end
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assign mem_req_valid_out_w = mem_req_valid_in;
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assign mem_req_rw_out_w = mem_req_rw_in;
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assign mem_req_byteen_out_w = mem_req_byteen_in;
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assign mem_req_data_out_w = mem_req_data_in;
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assign mem_req_tag_out_w = DST_TAG_WIDTH'(mem_req_tag_in);
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assign mem_req_ready_in = mem_req_ready_out_w;
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assign mem_rsp_valid_in_w = mem_rsp_valid_out;
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assign mem_rsp_data_in_w = mem_rsp_data_out;
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assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out);
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assign mem_rsp_ready_out = mem_rsp_ready_in_w;
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end
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VX_elastic_buffer #(
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.DATAW (1 + DST_DATA_SIZE + DST_ADDR_WIDTH + DST_DATA_WIDTH + DST_TAG_WIDTH),
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.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
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.OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF))
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) req_out_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (mem_req_valid_out_w),
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.ready_in (mem_req_ready_out_w),
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.data_in ({mem_req_rw_out_w, mem_req_byteen_out_w, mem_req_addr_out_w, mem_req_data_out_w, mem_req_tag_out_w}),
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.data_out ({mem_req_rw_out, mem_req_byteen_out, mem_req_addr_out, mem_req_data_out, mem_req_tag_out}),
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.valid_out (mem_req_valid_out),
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.ready_out (mem_req_ready_out)
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);
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VX_elastic_buffer #(
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.DATAW (SRC_DATA_WIDTH + SRC_TAG_WIDTH),
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.SIZE (`TO_OUT_BUF_SIZE(RSP_OUT_BUF)),
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.OUT_REG (`TO_OUT_BUF_REG(RSP_OUT_BUF))
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) rsp_in_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (mem_rsp_valid_in_w),
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.ready_in (mem_rsp_ready_in_w),
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.data_in ({mem_rsp_data_in_w, mem_rsp_tag_in_w}),
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.data_out ({mem_rsp_data_in, mem_rsp_tag_in}),
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.valid_out (mem_rsp_valid_in),
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.ready_out (mem_rsp_ready_in)
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);
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endmodule
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`TRACING_ON
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