mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
356 lines
No EOL
15 KiB
C++
356 lines
No EOL
15 KiB
C++
#include "vx_utils.h"
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#include <iostream>
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#include <fstream>
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#include <cstring>
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#include <vortex.h>
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#include <VX_config.h>
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#include <assert.h>
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uint64_t aligned_size(uint64_t size, uint64_t alignment) {
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assert(0 == (alignment & (alignment - 1)));
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return (size + alignment - 1) & ~(alignment - 1);
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}
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bool is_aligned(uint64_t addr, uint64_t alignment) {
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assert(0 == (alignment & (alignment - 1)));
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return 0 == (addr & (alignment - 1));
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}
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extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, uint64_t size) {
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int err = 0;
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if (NULL == content || 0 == size)
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return -1;
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uint32_t buffer_transfer_size = 65536; // 64 KB
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uint64_t kernel_base_addr;
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err = vx_dev_caps(device, VX_CAPS_KERNEL_BASE_ADDR, &kernel_base_addr);
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if (err != 0)
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return -1;
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// allocate device buffer
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vx_buffer_h buffer;
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err = vx_buf_alloc(device, buffer_transfer_size, &buffer);
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if (err != 0)
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return -1;
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// get buffer address
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auto buf_ptr = (uint8_t*)vx_host_ptr(buffer);
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//
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// upload content
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//
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uint64_t offset = 0;
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while (offset < size) {
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auto chunk_size = std::min<uint64_t>(buffer_transfer_size, size - offset);
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std::memcpy(buf_ptr, (uint8_t*)content + offset, chunk_size);
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/*printf("*** Upload Kernel to 0x%0x: data=", kernel_base_addr + offset);
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for (int i = 0, n = ((chunk_size+7)/8); i < n; ++i) {
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printf("%08x", ((uint64_t*)((uint8_t*)content + offset))[n-1-i]);
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}
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printf("\n");*/
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err = vx_copy_to_dev(buffer, kernel_base_addr + offset, chunk_size, 0);
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if (err != 0) {
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vx_buf_free(buffer);
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return err;
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}
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offset += chunk_size;
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}
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vx_buf_free(buffer);
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return 0;
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}
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extern int vx_upload_kernel_file(vx_device_h device, const char* filename) {
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std::ifstream ifs(filename);
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if (!ifs) {
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std::cout << "error: " << filename << " not found" << std::endl;
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return -1;
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}
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// read file content
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ifs.seekg(0, ifs.end);
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auto size = ifs.tellg();
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auto content = new char [size];
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ifs.seekg(0, ifs.beg);
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ifs.read(content, size);
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// upload
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int err = vx_upload_kernel_bytes(device, content, size);
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// release buffer
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delete[] content;
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return err;
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}
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/*static uint32_t get_csr_32(const uint32_t* buffer, int addr) {
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uint32_t value_lo = buffer[addr - CSR_MPM_BASE];
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return value_lo;
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}*/
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static uint64_t get_csr_64(const uint32_t* buffer, int addr) {
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uint32_t value_lo = buffer[addr - CSR_MPM_BASE];
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uint32_t value_hi = buffer[addr - CSR_MPM_BASE + 32];
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return (uint64_t(value_hi) << 32) | value_lo;
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}
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extern int vx_dump_perf(vx_device_h device, FILE* stream) {
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int ret = 0;
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uint64_t instrs = 0;
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uint64_t cycles = 0;
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#ifdef PERF_ENABLE
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// PERF: pipeline stalls
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uint64_t ibuffer_stalls = 0;
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uint64_t scoreboard_stalls = 0;
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uint64_t lsu_stalls = 0;
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uint64_t fpu_stalls = 0;
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uint64_t csr_stalls = 0;
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uint64_t alu_stalls = 0;
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uint64_t gpu_stalls = 0;
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// PERF: decode
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uint64_t loads = 0;
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uint64_t stores = 0;
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uint64_t branches = 0;
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// PERF: Icache
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uint64_t icache_reads = 0;
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uint64_t icache_read_misses = 0;
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// PERF: Dcache
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uint64_t dcache_reads = 0;
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uint64_t dcache_writes = 0;
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uint64_t dcache_read_misses = 0;
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uint64_t dcache_write_misses = 0;
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uint64_t dcache_bank_stalls = 0;
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uint64_t dcache_mshr_stalls = 0;
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// PERF: shared memory
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uint64_t smem_reads = 0;
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uint64_t smem_writes = 0;
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uint64_t smem_bank_stalls = 0;
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// PERF: memory
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uint64_t mem_reads = 0;
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uint64_t mem_writes = 0;
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uint64_t mem_lat = 0;
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#ifdef EXT_TEX_ENABLE
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// PERF: texunit
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uint64_t tex_mem_reads = 0;
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uint64_t tex_mem_lat = 0;
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#endif
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#endif
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uint64_t num_cores;
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ret = vx_dev_caps(device, VX_CAPS_MAX_CORES, &num_cores);
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if (ret != 0)
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return ret;
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vx_buffer_h staging_buf;
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ret = vx_buf_alloc(device, 64 * sizeof(uint32_t), &staging_buf);
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if (ret != 0)
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return ret;
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auto staging_ptr = (uint32_t*)vx_host_ptr(staging_buf);
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for (unsigned core_id = 0; core_id < num_cores; ++core_id) {
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ret = vx_copy_from_dev(staging_buf, IO_CSR_ADDR + 64 * sizeof(uint32_t) * core_id, 64 * sizeof(uint32_t), 0);
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if (ret != 0) {
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vx_buf_free(staging_buf);
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return ret;
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}
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uint64_t instrs_per_core = get_csr_64(staging_ptr, CSR_MINSTRET);
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uint64_t cycles_per_core = get_csr_64(staging_ptr, CSR_MCYCLE);
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float IPC = (float)(double(instrs_per_core) / double(cycles_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: instrs=%ld, cycles=%ld, IPC=%f\n", core_id, instrs_per_core, cycles_per_core, IPC);
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instrs += instrs_per_core;
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cycles = std::max<uint64_t>(cycles_per_core, cycles);
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#ifdef PERF_ENABLE
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// PERF: pipeline
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// ibuffer_stall
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uint64_t ibuffer_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_IBUF_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: ibuffer stalls=%ld\n", core_id, ibuffer_stalls_per_core);
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ibuffer_stalls += ibuffer_stalls_per_core;
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// scoreboard_stall
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uint64_t scoreboard_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_SCRB_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: scoreboard stalls=%ld\n", core_id, scoreboard_stalls_per_core);
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scoreboard_stalls += scoreboard_stalls_per_core;
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// alu_stall
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uint64_t alu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_ALU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: alu unit stalls=%ld\n", core_id, alu_stalls_per_core);
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alu_stalls += alu_stalls_per_core;
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// lsu_stall
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uint64_t lsu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_LSU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: lsu unit stalls=%ld\n", core_id, lsu_stalls_per_core);
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lsu_stalls += lsu_stalls_per_core;
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// csr_stall
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uint64_t csr_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_CSR_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: csr unit stalls=%ld\n", core_id, csr_stalls_per_core);
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csr_stalls += csr_stalls_per_core;
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// fpu_stall
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uint64_t fpu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_FPU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: fpu unit stalls=%ld\n", core_id, fpu_stalls_per_core);
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fpu_stalls += fpu_stalls_per_core;
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// gpu_stall
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uint64_t gpu_stalls_per_core = get_csr_64(staging_ptr, CSR_MPM_GPU_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: gpu unit stalls=%ld\n", core_id, gpu_stalls_per_core);
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gpu_stalls += gpu_stalls_per_core;
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// PERF: decode
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// loads
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uint64_t loads_per_core = get_csr_64(staging_ptr, CSR_MPM_LOADS);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: loads=%ld\n", core_id, loads_per_core);
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loads += loads_per_core;
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// stores
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uint64_t stores_per_core = get_csr_64(staging_ptr, CSR_MPM_STORES);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: stores=%ld\n", core_id, stores_per_core);
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stores += stores_per_core;
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// branches
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uint64_t branches_per_core = get_csr_64(staging_ptr, CSR_MPM_BRANCHES);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: branches=%ld\n", core_id, branches_per_core);
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branches += branches_per_core;
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// PERF: Icache
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// total reads
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uint64_t icache_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_ICACHE_READS);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache reads=%ld\n", core_id, icache_reads_per_core);
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icache_reads += icache_reads_per_core;
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// read misses
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uint64_t icache_miss_r_per_core = get_csr_64(staging_ptr, CSR_MPM_ICACHE_MISS_R);
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int icache_read_hit_ratio = (int)((1.0 - (double(icache_miss_r_per_core) / double(icache_reads_per_core))) * 100);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: icache misses=%ld (hit ratio=%d%%)\n", core_id, icache_miss_r_per_core, icache_read_hit_ratio);
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icache_read_misses += icache_miss_r_per_core;
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// PERF: Dcache
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// total reads
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uint64_t dcache_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_READS);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache reads=%ld\n", core_id, dcache_reads_per_core);
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dcache_reads += dcache_reads_per_core;
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// total write
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uint64_t dcache_writes_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_WRITES);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache writes=%ld\n", core_id, dcache_writes_per_core);
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dcache_writes += dcache_writes_per_core;
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// read misses
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uint64_t dcache_miss_r_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_MISS_R);
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int dcache_read_hit_ratio = (int)((1.0 - (double(dcache_miss_r_per_core) / double(dcache_reads_per_core))) * 100);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache read misses=%ld (hit ratio=%d%%)\n", core_id, dcache_miss_r_per_core, dcache_read_hit_ratio);
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dcache_read_misses += dcache_miss_r_per_core;
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// read misses
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uint64_t dcache_miss_w_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_MISS_W);
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int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_miss_w_per_core) / double(dcache_writes_per_core))) * 100);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache write misses=%ld (hit ratio=%d%%)\n", core_id, dcache_miss_w_per_core, dcache_write_hit_ratio);
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dcache_write_misses += dcache_miss_w_per_core;
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// bank_stalls
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uint64_t dcache_bank_st_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_BANK_ST);
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int dcache_bank_utilization = (int)((double(dcache_reads_per_core + dcache_writes_per_core) / double(dcache_reads_per_core + dcache_writes_per_core + dcache_bank_st_per_core)) * 100);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache bank stalls=%ld (utilization=%d%%)\n", core_id, dcache_bank_st_per_core, dcache_bank_utilization);
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dcache_bank_stalls += dcache_bank_st_per_core;
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// mshr_stalls
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uint64_t dcache_mshr_st_per_core = get_csr_64(staging_ptr, CSR_MPM_DCACHE_MSHR_ST);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: dcache mshr stalls=%ld\n", core_id, dcache_mshr_st_per_core);
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dcache_mshr_stalls += dcache_mshr_st_per_core;
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// PERF: SMEM
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// total reads
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uint64_t smem_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_SMEM_READS);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: smem reads=%ld\n", core_id, smem_reads_per_core);
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smem_reads += smem_reads_per_core;
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// total write
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uint64_t smem_writes_per_core = get_csr_64(staging_ptr, CSR_MPM_SMEM_WRITES);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: smem writes=%ld\n", core_id, smem_writes_per_core);
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smem_writes += smem_writes_per_core;
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// bank_stalls
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uint64_t smem_bank_st_per_core = get_csr_64(staging_ptr, CSR_MPM_SMEM_BANK_ST);
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int smem_bank_utilization = (int)((double(smem_reads_per_core + smem_writes_per_core) / double(smem_reads_per_core + smem_writes_per_core + smem_bank_st_per_core)) * 100);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: smem bank stalls=%ld (utilization=%d%%)\n", core_id, smem_bank_st_per_core, smem_bank_utilization);
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smem_bank_stalls += smem_bank_st_per_core;
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// PERF: memory
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uint64_t mem_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_MEM_READS);
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uint64_t mem_writes_per_core = get_csr_64(staging_ptr, CSR_MPM_MEM_WRITES);
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uint64_t mem_lat_per_core = get_csr_64(staging_ptr, CSR_MPM_MEM_LAT);
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int mem_avg_lat = (int)(double(mem_lat_per_core) / double(mem_reads_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: memory requests=%ld (reads=%ld, writes=%ld)\n", core_id, (mem_reads_per_core + mem_writes_per_core), mem_reads_per_core, mem_writes_per_core);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: memory latency=%d cycles\n", core_id, mem_avg_lat);
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mem_reads += mem_reads_per_core;
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mem_writes += mem_writes_per_core;
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mem_lat += mem_lat_per_core;
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#ifdef EXT_TEX_ENABLE
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// total reads
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uint64_t tex_reads_per_core = get_csr_64(staging_ptr, CSR_MPM_TEX_READS);
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if (num_cores > 1) fprintf(stream, "PERF: core%d: tex memory reads=%ld\n", core_id, tex_reads_per_core);
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tex_mem_reads += tex_reads_per_core;
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// read latency
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uint64_t tex_lat_per_core = get_csr_64(staging_ptr, CSR_MPM_TEX_LAT);
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int tex_avg_lat = (int)(double(tex_lat_per_core) / double(tex_reads_per_core));
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if (num_cores > 1) fprintf(stream, "PERF: core%d: tex memory latency=%d cycles\n", core_id, tex_avg_lat);
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tex_mem_lat += tex_lat_per_core;
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#endif
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#endif
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}
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float IPC = (float)(double(instrs) / double(cycles));
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fprintf(stream, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC);
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#ifdef PERF_ENABLE
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int icache_read_hit_ratio = (int)((1.0 - (double(icache_read_misses) / double(icache_reads))) * 100);
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int dcache_read_hit_ratio = (int)((1.0 - (double(dcache_read_misses) / double(dcache_reads))) * 100);
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int dcache_write_hit_ratio = (int)((1.0 - (double(dcache_write_misses) / double(dcache_writes))) * 100);
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int dcache_bank_utilization = (int)((double(dcache_reads + dcache_writes) / double(dcache_reads + dcache_writes + dcache_bank_stalls)) * 100);
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int smem_bank_utilization = (int)((double(smem_reads + smem_writes) / double(smem_reads + smem_writes + smem_bank_stalls)) * 100);
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int mem_avg_lat = (int)(double(mem_lat) / double(mem_reads));
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fprintf(stream, "PERF: ibuffer stalls=%ld\n", ibuffer_stalls);
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fprintf(stream, "PERF: scoreboard stalls=%ld\n", scoreboard_stalls);
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fprintf(stream, "PERF: alu unit stalls=%ld\n", alu_stalls);
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fprintf(stream, "PERF: lsu unit stalls=%ld\n", lsu_stalls);
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fprintf(stream, "PERF: csr unit stalls=%ld\n", csr_stalls);
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fprintf(stream, "PERF: fpu unit stalls=%ld\n", fpu_stalls);
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fprintf(stream, "PERF: gpu unit stalls=%ld\n", gpu_stalls);
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fprintf(stream, "PERF: loads=%ld\n", loads);
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fprintf(stream, "PERF: stores=%ld\n", stores);
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fprintf(stream, "PERF: branches=%ld\n", branches);
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fprintf(stream, "PERF: icache reads=%ld\n", icache_reads);
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fprintf(stream, "PERF: icache read misses=%ld (hit ratio=%d%%)\n", icache_read_misses, icache_read_hit_ratio);
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fprintf(stream, "PERF: dcache reads=%ld\n", dcache_reads);
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fprintf(stream, "PERF: dcache writes=%ld\n", dcache_writes);
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fprintf(stream, "PERF: dcache read misses=%ld (hit ratio=%d%%)\n", dcache_read_misses, dcache_read_hit_ratio);
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fprintf(stream, "PERF: dcache write misses=%ld (hit ratio=%d%%)\n", dcache_write_misses, dcache_write_hit_ratio);
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fprintf(stream, "PERF: dcache bank stalls=%ld (utilization=%d%%)\n", dcache_bank_stalls, dcache_bank_utilization);
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fprintf(stream, "PERF: dcache mshr stalls=%ld\n", dcache_mshr_stalls);
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fprintf(stream, "PERF: smem reads=%ld\n", smem_reads);
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fprintf(stream, "PERF: smem writes=%ld\n", smem_writes);
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fprintf(stream, "PERF: smem bank stalls=%ld (utilization=%d%%)\n", smem_bank_stalls, smem_bank_utilization);
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fprintf(stream, "PERF: memory requests=%ld (reads=%ld, writes=%ld)\n", (mem_reads + mem_writes), mem_reads, mem_writes);
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fprintf(stream, "PERF: memory average latency=%d cycles\n", mem_avg_lat);
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#ifdef EXT_TEX_ENABLE
|
|
int tex_avg_lat = (int)(double(tex_mem_lat) / double(tex_mem_reads));
|
|
fprintf(stream, "PERF: tex memory reads=%ld\n", tex_mem_reads);
|
|
fprintf(stream, "PERF: tex memory latency=%d cycles\n", tex_avg_lat);
|
|
#endif
|
|
#endif
|
|
|
|
// release allocated resources
|
|
vx_buf_free(staging_buf);
|
|
|
|
return ret;
|
|
}
|
|
|
|
// Deprecated API functions
|
|
|
|
extern int vx_alloc_shared_mem(vx_device_h hdevice, uint64_t size, vx_buffer_h* hbuffer) {
|
|
return vx_buf_alloc(hdevice, size, hbuffer);
|
|
}
|
|
|
|
extern int vx_buf_release(vx_buffer_h hbuffer) {
|
|
return vx_buf_free(hbuffer);
|
|
}
|
|
|
|
extern int vx_alloc_dev_mem(vx_device_h hdevice, uint64_t size, uint64_t* dev_maddr) {
|
|
return vx_mem_alloc(hdevice, size, dev_maddr);
|
|
} |