mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-21 04:17:53 -04:00
265 lines
No EOL
13 KiB
Systemverilog
265 lines
No EOL
13 KiB
Systemverilog
`include "VX_define.vh"
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module VX_csr_data #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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`ifdef EXT_TEX_ENABLE
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VX_perf_tex_if.slave perf_tex_if,
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`endif
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VX_perf_memsys_if.slave perf_memsys_if,
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VX_perf_pipeline_if.slave perf_pipeline_if,
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`endif
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VX_cmt_to_csr_if.slave cmt_to_csr_if,
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VX_fetch_to_csr_if.slave fetch_to_csr_if,
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`ifdef EXT_F_ENABLE
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VX_fpu_to_csr_if.slave fpu_to_csr_if,
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`endif
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`ifdef EXT_TEX_ENABLE
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VX_tex_csr_if.master tex_csr_if,
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`endif
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input wire read_enable,
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input wire [`UUID_BITS-1:0] read_uuid,
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input wire[`CSR_ADDR_BITS-1:0] read_addr,
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input wire[`NW_BITS-1:0] read_wid,
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output wire[31:0] read_data,
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input wire write_enable,
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input wire [`UUID_BITS-1:0] write_uuid,
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input wire[`CSR_ADDR_BITS-1:0] write_addr,
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input wire[`NW_BITS-1:0] write_wid,
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input wire[31:0] write_data,
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input wire busy
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);
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import fpu_types::*;
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reg [`CSR_WIDTH-1:0] csr_satp;
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reg [`CSR_WIDTH-1:0] csr_mstatus;
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reg [`CSR_WIDTH-1:0] csr_medeleg;
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reg [`CSR_WIDTH-1:0] csr_mideleg;
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reg [`CSR_WIDTH-1:0] csr_mie;
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reg [`CSR_WIDTH-1:0] csr_mtvec;
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reg [`CSR_WIDTH-1:0] csr_mepc;
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reg [`CSR_WIDTH-1:0] csr_pmpcfg [0:0];
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reg [`CSR_WIDTH-1:0] csr_pmpaddr [0:0];
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reg [63:0] csr_cycle;
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reg [63:0] csr_instret;
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reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FFLAGS_BITS-1:0] fcsr;
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always @(posedge clk) begin
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if (reset) begin
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fcsr <= '0;
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end else begin
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`ifdef EXT_F_ENABLE
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if (fpu_to_csr_if.write_enable) begin
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fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFLAGS_BITS-1:0]
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| fpu_to_csr_if.write_fflags;
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end
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`endif
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if (write_enable) begin
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case (write_addr)
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`CSR_FFLAGS: fcsr[write_wid][`FFLAGS_BITS-1:0] <= write_data[`FFLAGS_BITS-1:0];
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`CSR_FRM: fcsr[write_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS] <= write_data[`INST_FRM_BITS-1:0];
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`CSR_FCSR: fcsr[write_wid] <= write_data[`FFLAGS_BITS+`INST_FRM_BITS-1:0];
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`CSR_SATP: csr_satp <= write_data[`CSR_WIDTH-1:0];
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`CSR_MSTATUS: csr_mstatus <= write_data[`CSR_WIDTH-1:0];
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`CSR_MEDELEG: csr_medeleg <= write_data[`CSR_WIDTH-1:0];
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`CSR_MIDELEG: csr_mideleg <= write_data[`CSR_WIDTH-1:0];
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`CSR_MIE: csr_mie <= write_data[`CSR_WIDTH-1:0];
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`CSR_MTVEC: csr_mtvec <= write_data[`CSR_WIDTH-1:0];
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`CSR_MEPC: csr_mepc <= write_data[`CSR_WIDTH-1:0];
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`CSR_PMPCFG0: csr_pmpcfg[0] <= write_data[`CSR_WIDTH-1:0];
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`CSR_PMPADDR0: csr_pmpaddr[0] <= write_data[`CSR_WIDTH-1:0];
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default: begin
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`ifdef EXT_TEX_ENABLE
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`ASSERT((write_addr == `CSR_TEX_UNIT)
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|| (write_addr >= `CSR_TEX_STATE_BEGIN
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&& write_addr < `CSR_TEX_STATE_END),
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("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid));
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`else
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`ASSERT(~write_enable, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid));
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`endif
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end
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endcase
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end
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end
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end
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`UNUSED_VAR (write_data)
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// TEX CSRs
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`ifdef EXT_TEX_ENABLE
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assign tex_csr_if.write_enable = write_enable;
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assign tex_csr_if.write_addr = write_addr;
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assign tex_csr_if.write_data = write_data;
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assign tex_csr_if.write_uuid = write_uuid;
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`endif
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always @(posedge clk) begin
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if (reset) begin
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csr_cycle <= 0;
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csr_instret <= 0;
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end else begin
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if (busy) begin
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csr_cycle <= csr_cycle + 1;
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end
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if (cmt_to_csr_if.valid) begin
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csr_instret <= csr_instret + 64'(cmt_to_csr_if.commit_size);
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end
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end
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end
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reg [31:0] read_data_r;
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reg read_addr_valid_r;
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always @(*) begin
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read_data_r = 'x;
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read_addr_valid_r = 1;
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case (read_addr)
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`CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFLAGS_BITS-1:0]);
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`CSR_FRM : read_data_r = 32'(fcsr[read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS]);
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`CSR_FCSR : read_data_r = 32'(fcsr[read_wid]);
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`CSR_WTID ,
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`CSR_LTID ,
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`CSR_LWID : read_data_r = 32'(read_wid);
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`CSR_GTID ,
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/*`CSR_MHARTID ,*/
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`CSR_GWID : read_data_r = CORE_ID * `NUM_WARPS + 32'(read_wid);
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`CSR_GCID : read_data_r = CORE_ID;
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`CSR_TMASK : read_data_r = 32'(fetch_to_csr_if.thread_masks[read_wid]);
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`CSR_NT : read_data_r = `NUM_THREADS;
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`CSR_NW : read_data_r = `NUM_WARPS;
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`CSR_NC : read_data_r = `NUM_CORES * `NUM_CLUSTERS;
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`CSR_MCYCLE : read_data_r = csr_cycle[31:0];
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`CSR_MCYCLE_H : read_data_r = 32'(csr_cycle[`PERF_CTR_BITS-1:32]);
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`CSR_MINSTRET : read_data_r = csr_instret[31:0];
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`CSR_MINSTRET_H : read_data_r = 32'(csr_instret[`PERF_CTR_BITS-1:32]);
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`ifdef PERF_ENABLE
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// PERF: pipeline
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`CSR_MPM_IBUF_ST : read_data_r = perf_pipeline_if.ibf_stalls[31:0];
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`CSR_MPM_IBUF_ST_H : read_data_r = 32'(perf_pipeline_if.ibf_stalls[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_SCRB_ST : read_data_r = perf_pipeline_if.scb_stalls[31:0];
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`CSR_MPM_SCRB_ST_H : read_data_r = 32'(perf_pipeline_if.scb_stalls[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_ALU_ST : read_data_r = perf_pipeline_if.alu_stalls[31:0];
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`CSR_MPM_ALU_ST_H : read_data_r = 32'(perf_pipeline_if.alu_stalls[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_LSU_ST : read_data_r = perf_pipeline_if.lsu_stalls[31:0];
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`CSR_MPM_LSU_ST_H : read_data_r = 32'(perf_pipeline_if.lsu_stalls[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_CSR_ST : read_data_r = perf_pipeline_if.csr_stalls[31:0];
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`CSR_MPM_CSR_ST_H : read_data_r = 32'(perf_pipeline_if.csr_stalls[`PERF_CTR_BITS-1:32]);
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`ifdef EXT_F_ENABLE
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`CSR_MPM_FPU_ST : read_data_r = perf_pipeline_if.fpu_stalls[31:0];
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`CSR_MPM_FPU_ST_H : read_data_r = 32'(perf_pipeline_if.fpu_stalls[`PERF_CTR_BITS-1:32]);
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`else
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`CSR_MPM_FPU_ST : read_data_r = '0;
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`CSR_MPM_FPU_ST_H : read_data_r = '0;
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`endif
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`CSR_MPM_GPU_ST : read_data_r = perf_pipeline_if.gpu_stalls[31:0];
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`CSR_MPM_GPU_ST_H : read_data_r = 32'(perf_pipeline_if.gpu_stalls[`PERF_CTR_BITS-1:32]);
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// PERF: decode
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`CSR_MPM_LOADS : read_data_r = perf_pipeline_if.loads[31:0];
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`CSR_MPM_LOADS_H : read_data_r = 32'(perf_pipeline_if.loads[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_STORES : read_data_r = perf_pipeline_if.stores[31:0];
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`CSR_MPM_STORES_H : read_data_r = 32'(perf_pipeline_if.stores[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_BRANCHES : read_data_r = perf_pipeline_if.branches[31:0];
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`CSR_MPM_BRANCHES_H : read_data_r = 32'(perf_pipeline_if.branches[`PERF_CTR_BITS-1:32]);
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// PERF: icache
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`CSR_MPM_ICACHE_READS : read_data_r = perf_memsys_if.icache_reads[31:0];
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`CSR_MPM_ICACHE_READS_H : read_data_r = 32'(perf_memsys_if.icache_reads[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_ICACHE_MISS_R : read_data_r = perf_memsys_if.icache_read_misses[31:0];
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`CSR_MPM_ICACHE_MISS_R_H : read_data_r = 32'(perf_memsys_if.icache_read_misses[`PERF_CTR_BITS-1:32]);
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// PERF: dcache
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`CSR_MPM_DCACHE_READS : read_data_r = perf_memsys_if.dcache_reads[31:0];
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`CSR_MPM_DCACHE_READS_H : read_data_r = 32'(perf_memsys_if.dcache_reads[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_DCACHE_WRITES : read_data_r = perf_memsys_if.dcache_writes[31:0];
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`CSR_MPM_DCACHE_WRITES_H : read_data_r = 32'(perf_memsys_if.dcache_writes[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_DCACHE_MISS_R : read_data_r = perf_memsys_if.dcache_read_misses[31:0];
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`CSR_MPM_DCACHE_MISS_R_H : read_data_r = 32'(perf_memsys_if.dcache_read_misses[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_DCACHE_MISS_W : read_data_r = perf_memsys_if.dcache_write_misses[31:0];
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`CSR_MPM_DCACHE_MISS_W_H : read_data_r = 32'(perf_memsys_if.dcache_write_misses[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_DCACHE_BANK_ST : read_data_r = perf_memsys_if.dcache_bank_stalls[31:0];
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`CSR_MPM_DCACHE_BANK_ST_H : read_data_r = 32'(perf_memsys_if.dcache_bank_stalls[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_DCACHE_MSHR_ST : read_data_r = perf_memsys_if.dcache_mshr_stalls[31:0];
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`CSR_MPM_DCACHE_MSHR_ST_H : read_data_r = 32'(perf_memsys_if.dcache_mshr_stalls[`PERF_CTR_BITS-1:32]);
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// PERF: smem
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`CSR_MPM_SMEM_READS : read_data_r = perf_memsys_if.smem_reads[31:0];
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`CSR_MPM_SMEM_READS_H : read_data_r = 32'(perf_memsys_if.smem_reads[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_SMEM_WRITES : read_data_r = perf_memsys_if.smem_writes[31:0];
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`CSR_MPM_SMEM_WRITES_H : read_data_r = 32'(perf_memsys_if.smem_writes[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_SMEM_BANK_ST : read_data_r = perf_memsys_if.smem_bank_stalls[31:0];
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`CSR_MPM_SMEM_BANK_ST_H : read_data_r = 32'(perf_memsys_if.smem_bank_stalls[`PERF_CTR_BITS-1:32]);
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// PERF: memory
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`CSR_MPM_MEM_READS : read_data_r = perf_memsys_if.mem_reads[31:0];
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`CSR_MPM_MEM_READS_H : read_data_r = 32'(perf_memsys_if.mem_reads[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_MEM_WRITES : read_data_r = perf_memsys_if.mem_writes[31:0];
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`CSR_MPM_MEM_WRITES_H : read_data_r = 32'(perf_memsys_if.mem_writes[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_MEM_LAT : read_data_r = perf_memsys_if.mem_latency[31:0];
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`CSR_MPM_MEM_LAT_H : read_data_r = 32'(perf_memsys_if.mem_latency[`PERF_CTR_BITS-1:32]);
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`ifdef EXT_TEX_ENABLE
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// PERF: texunit
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`CSR_MPM_TEX_READS : read_data_r = perf_tex_if.mem_reads[31:0];
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`CSR_MPM_TEX_READS_H : read_data_r = 32'(perf_tex_if.mem_reads[`PERF_CTR_BITS-1:32]);
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`CSR_MPM_TEX_LAT : read_data_r = perf_tex_if.mem_latency[31:0];
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`CSR_MPM_TEX_LAT_H : read_data_r = 32'(perf_tex_if.mem_latency[`PERF_CTR_BITS-1:32]);
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`endif
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// PERF: reserved
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`CSR_MPM_RESERVED : read_data_r = '0;
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`CSR_MPM_RESERVED_H : read_data_r = '0;
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`endif
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`CSR_SATP : read_data_r = 32'(csr_satp);
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`CSR_MSTATUS : read_data_r = 32'(csr_mstatus);
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`CSR_MISA : read_data_r = `ISA_CODE;
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`CSR_MEDELEG : read_data_r = 32'(csr_medeleg);
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`CSR_MIDELEG : read_data_r = 32'(csr_mideleg);
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`CSR_MIE : read_data_r = 32'(csr_mie);
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`CSR_MTVEC : read_data_r = 32'(csr_mtvec);
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`CSR_MEPC : read_data_r = 32'(csr_mepc);
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`CSR_PMPCFG0 : read_data_r = 32'(csr_pmpcfg[0]);
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`CSR_PMPADDR0 : read_data_r = 32'(csr_pmpaddr[0]);
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`CSR_MVENDORID : read_data_r = `VENDOR_ID;
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`CSR_MARCHID : read_data_r = `ARCHITECTURE_ID;
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`CSR_MIMPID : read_data_r = `IMPLEMENTATION_ID;
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default: begin
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if ((read_addr >= `CSR_MPM_BASE && read_addr < (`CSR_MPM_BASE + 32))
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|| (read_addr >= `CSR_MPM_BASE_H && read_addr < (`CSR_MPM_BASE_H + 32))) begin
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read_addr_valid_r = 1;
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end else
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`ifdef EXT_TEX_ENABLE
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if ((read_addr == `CSR_TEX_UNIT)
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|| (read_addr >= `CSR_TEX_STATE_BEGIN
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&& read_addr < `CSR_TEX_STATE_END)) begin
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read_addr_valid_r = 1;
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end else
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`endif
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read_addr_valid_r = 0;
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end
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endcase
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end
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`RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("%t: *** invalid CSR read address: %0h (#%0d)", $time, read_addr, read_uuid))
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assign read_data = read_data_r;
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`ifdef EXT_F_ENABLE
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assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`INST_FRM_BITS+`FFLAGS_BITS-1:`FFLAGS_BITS];
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`endif
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endmodule |