mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-22 12:57:41 -04:00
495 lines
No EOL
19 KiB
Systemverilog
495 lines
No EOL
19 KiB
Systemverilog
`include "VX_define.vh"
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`ifdef DBG_TRACE_CORE_PIPELINE
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`include "VX_trace_instr.vh"
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`endif
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`ifdef EXT_F_ENABLE
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`define USED_IREG(r) \
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r``_r = {1'b0, ``r}
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`define USED_FREG(r) \
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r``_r = {1'b1, ``r}
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`else
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`define USED_IREG(r) \
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r``_r = ``r
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`endif
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module VX_decode #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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VX_perf_pipeline_if.decode perf_decode_if,
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`endif
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// inputs
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VX_ifetch_rsp_if.slave ifetch_rsp_if,
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// outputs
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VX_decode_if.master decode_if,
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VX_wstall_if.master wstall_if,
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VX_join_if.master join_if
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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reg [`EX_BITS-1:0] ex_type;
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reg [`INST_OP_BITS-1:0] op_type;
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reg [`INST_MOD_BITS-1:0] op_mod;
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reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r;
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reg [31:0] imm;
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reg use_rd, use_PC, use_imm;
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reg is_join, is_wstall;
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wire [31:0] instr = ifetch_rsp_if.data;
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wire [6:0] opcode = instr[6:0];
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wire [1:0] func2 = instr[26:25];
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wire [2:0] func3 = instr[14:12];
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wire [6:0] func7 = instr[31:25];
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wire [11:0] u_12 = instr[31:20];
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wire [4:0] rd = instr[11:7];
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rs3 = instr[31:27];
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wire [19:0] upper_imm = {func7, rs2, rs1, func3};
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wire [11:0] alu_imm = (func3[0] && ~func3[1]) ? {{7{1'b0}}, rs2} : u_12;
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wire [11:0] s_imm = {func7, rd};
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wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
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wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
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`UNUSED_VAR (rs3)
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always @(*) begin
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ex_type = 0;
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op_type = 'x;
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op_mod = 0;
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rd_r = 0;
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rs1_r = 0;
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rs2_r = 0;
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rs3_r = 0;
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imm = 'x;
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use_imm = 0;
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use_PC = 0;
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use_rd = 0;
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is_join = 0;
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is_wstall = 0;
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case (opcode)
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`INST_I: begin
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ex_type = `EX_ALU;
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case (func3)
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3'h0: op_type = `INST_OP_BITS'(`INST_ALU_ADD);
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3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL);
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3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT);
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3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU);
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3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR);
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3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL);
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3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR);
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3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND);
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default:;
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endcase
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use_rd = 1;
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use_imm = 1;
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imm = {{20{alu_imm[11]}}, alu_imm};
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`USED_IREG (rd);
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`USED_IREG (rs1);
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end
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`INST_R: begin
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ex_type = `EX_ALU;
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`ifdef EXT_F_ENABLE
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if (func7[0]) begin
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case (func3)
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3'h0: op_type = `INST_OP_BITS'(`INST_MUL_MUL);
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3'h1: op_type = `INST_OP_BITS'(`INST_MUL_MULH);
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3'h2: op_type = `INST_OP_BITS'(`INST_MUL_MULHSU);
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3'h3: op_type = `INST_OP_BITS'(`INST_MUL_MULHU);
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3'h4: op_type = `INST_OP_BITS'(`INST_MUL_DIV);
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3'h5: op_type = `INST_OP_BITS'(`INST_MUL_DIVU);
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3'h6: op_type = `INST_OP_BITS'(`INST_MUL_REM);
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3'h7: op_type = `INST_OP_BITS'(`INST_MUL_REMU);
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default:;
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endcase
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op_mod = 2;
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end else
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`endif
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begin
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case (func3)
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3'h0: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SUB) : `INST_OP_BITS'(`INST_ALU_ADD);
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3'h1: op_type = `INST_OP_BITS'(`INST_ALU_SLL);
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3'h2: op_type = `INST_OP_BITS'(`INST_ALU_SLT);
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3'h3: op_type = `INST_OP_BITS'(`INST_ALU_SLTU);
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3'h4: op_type = `INST_OP_BITS'(`INST_ALU_XOR);
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3'h5: op_type = (func7[5]) ? `INST_OP_BITS'(`INST_ALU_SRA) : `INST_OP_BITS'(`INST_ALU_SRL);
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3'h6: op_type = `INST_OP_BITS'(`INST_ALU_OR);
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3'h7: op_type = `INST_OP_BITS'(`INST_ALU_AND);
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default:;
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endcase
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end
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use_rd = 1;
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`USED_IREG (rd);
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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end
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`INST_LUI: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_ALU_LUI);
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use_rd = 1;
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use_imm = 1;
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imm = {upper_imm, 12'(0)};
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`USED_IREG (rd);
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rs1_r = 0;
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end
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`INST_AUIPC: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_ALU_AUIPC);
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use_rd = 1;
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use_imm = 1;
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use_PC = 1;
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imm = {upper_imm, 12'(0)};
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`USED_IREG (rd);
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end
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`INST_JAL: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_BR_JAL);
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op_mod = 1;
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use_rd = 1;
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use_imm = 1;
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use_PC = 1;
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is_wstall = 1;
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imm = {{11{jal_imm[20]}}, jal_imm};
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`USED_IREG (rd);
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end
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`INST_JALR: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_BR_JALR);
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op_mod = 1;
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use_rd = 1;
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use_imm = 1;
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is_wstall = 1;
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imm = {{20{u_12[11]}}, u_12};
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`USED_IREG (rd);
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`USED_IREG (rs1);
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end
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`INST_B: begin
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ex_type = `EX_ALU;
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case (func3)
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3'h0: op_type = `INST_OP_BITS'(`INST_BR_EQ);
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3'h1: op_type = `INST_OP_BITS'(`INST_BR_NE);
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3'h4: op_type = `INST_OP_BITS'(`INST_BR_LT);
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3'h5: op_type = `INST_OP_BITS'(`INST_BR_GE);
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3'h6: op_type = `INST_OP_BITS'(`INST_BR_LTU);
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3'h7: op_type = `INST_OP_BITS'(`INST_BR_GEU);
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default:;
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endcase
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op_mod = 1;
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use_imm = 1;
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use_PC = 1;
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is_wstall = 1;
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imm = {{19{b_imm[12]}}, b_imm};
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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end
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`INST_FENCE: begin
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ex_type = `EX_LSU;
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op_mod = `INST_MOD_BITS'(1);
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end
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`INST_SYS : begin
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if (func3[1:0] != 0) begin
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ex_type = `EX_CSR;
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op_type = `INST_OP_BITS'(func3[1:0]);
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use_rd = 1;
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use_imm = func3[2];
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imm[`CSR_ADDR_BITS-1:0] = u_12; // addr
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`USED_IREG (rd);
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if (func3[2]) begin
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imm[`CSR_ADDR_BITS +: `NRI_BITS] = rs1; // imm
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end else begin
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`USED_IREG (rs1);
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end
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end else begin
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ex_type = `EX_ALU;
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case (u_12)
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12'h000: op_type = `INST_OP_BITS'(`INST_BR_ECALL);
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12'h001: op_type = `INST_OP_BITS'(`INST_BR_EBREAK);
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12'h002: op_type = `INST_OP_BITS'(`INST_BR_URET);
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12'h102: op_type = `INST_OP_BITS'(`INST_BR_SRET);
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12'h302: op_type = `INST_OP_BITS'(`INST_BR_MRET);
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default:;
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endcase
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op_mod = 1;
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use_rd = 1;
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use_imm = 1;
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use_PC = 1;
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is_wstall = 1;
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imm = 32'd4;
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`USED_IREG (rd);
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end
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end
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`ifdef EXT_F_ENABLE
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`INST_FL,
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`endif
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`INST_L: begin
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ex_type = `EX_LSU;
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op_type = `INST_OP_BITS'({1'b0, func3});
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use_rd = 1;
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imm = {{20{u_12[11]}}, u_12};
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`ifdef EXT_F_ENABLE
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if (opcode[2]) begin
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`USED_FREG (rd);
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end else
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`endif
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`USED_IREG (rd);
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`USED_IREG (rs1);
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end
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`ifdef EXT_F_ENABLE
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`INST_FS,
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`endif
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`INST_S: begin
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ex_type = `EX_LSU;
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op_type = `INST_OP_BITS'({1'b1, func3});
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imm = {{20{s_imm[11]}}, s_imm};
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`USED_IREG (rs1);
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`ifdef EXT_F_ENABLE
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if (opcode[2]) begin
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`USED_FREG (rs2);
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end else
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`endif
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`USED_IREG (rs2);
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end
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`ifdef EXT_F_ENABLE
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`INST_FMADD,
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`INST_FMSUB,
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`INST_FNMSUB,
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`INST_FNMADD: begin
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ex_type = `EX_FPU;
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op_type = `INST_OP_BITS'(opcode[3:0]);
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op_mod = func3;
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use_rd = 1;
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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`USED_FREG (rs3);
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end
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`INST_FCI: begin
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ex_type = `EX_FPU;
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op_mod = func3;
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use_rd = 1;
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case (func7)
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7'h00, // FADD
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7'h04, // FSUB
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7'h08, // FMUL
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7'h0C: begin // FDIV
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op_type = `INST_OP_BITS'(func7[3:0]);
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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7'h2C: begin
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op_type = `INST_OP_BITS'(`INST_FPU_SQRT);
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`USED_FREG (rd);
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`USED_FREG (rs1);
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end
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7'h50: begin
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op_type = `INST_OP_BITS'(`INST_FPU_CMP);
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`USED_IREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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7'h60: begin
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op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTWUS) : `INST_OP_BITS'(`INST_FPU_CVTWS);
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`USED_IREG (rd);
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`USED_FREG (rs1);
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end
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7'h68: begin
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op_type = (instr[20]) ? `INST_OP_BITS'(`INST_FPU_CVTSWU) : `INST_OP_BITS'(`INST_FPU_CVTSW);
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`USED_FREG (rd);
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`USED_IREG (rs1);
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end
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7'h10: begin
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// FSGNJ=0, FSGNJN=1, FSGNJX=2
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = {1'b0, func3[1:0]};
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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7'h14: begin
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// FMIN=3, FMAX=4
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = func3[0] ? 4 : 3;
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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7'h70: begin
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if (func3[0]) begin
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// FCLASS
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op_type = `INST_OP_BITS'(`INST_FPU_CLASS);
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end else begin
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// FMV.X.W=5
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = 5;
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end
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`USED_IREG (rd);
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`USED_FREG (rs1);
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end
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7'h78: begin
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// FMV.W.X=6
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = 6;
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`USED_FREG (rd);
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`USED_IREG (rs1);
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end
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default:;
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endcase
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end
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`endif
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`INST_GPGPU: begin
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ex_type = `EX_GPU;
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case (func3)
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3'h0: begin
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op_type = rs2[0] ? `INST_OP_BITS'(`INST_GPU_PRED) : `INST_OP_BITS'(`INST_GPU_TMC);
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is_wstall = 1;
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`USED_IREG (rs1);
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end
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3'h1: begin
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op_type = `INST_OP_BITS'(`INST_GPU_WSPAWN);
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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end
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3'h2: begin
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op_type = `INST_OP_BITS'(`INST_GPU_SPLIT);
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is_wstall = 1;
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`USED_IREG (rs1);
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end
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3'h3: begin
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op_type = `INST_OP_BITS'(`INST_GPU_JOIN);
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is_join = 1;
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end
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3'h4: begin
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op_type = `INST_OP_BITS'(`INST_GPU_BAR);
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is_wstall = 1;
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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end
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3'h5: begin
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ex_type = `EX_LSU;
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op_type = `INST_OP_BITS'(`INST_LSU_LW);
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op_mod = `INST_MOD_BITS'(2);
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`USED_IREG (rs1);
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end
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default:;
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endcase
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end
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`INST_GPU: begin
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case (func3)
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`ifdef EXT_TEX_ENABLE
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3'h0: begin
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ex_type = `EX_GPU;
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op_type = `INST_OP_BITS'(`INST_GPU_TEX);
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op_mod = `INST_MOD_BITS'(func2);
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use_rd = 1;
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`USED_IREG (rd);
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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`USED_IREG (rs3);
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end
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`endif
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default:;
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endcase
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end
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default:;
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endcase
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end
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`UNUSED_VAR (func2)
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// disable write to integer register r0
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wire wb = use_rd && (| rd_r);
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assign decode_if.valid = ifetch_rsp_if.valid;
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assign decode_if.uuid = ifetch_rsp_if.uuid;
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assign decode_if.wid = ifetch_rsp_if.wid;
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assign decode_if.tmask = ifetch_rsp_if.tmask;
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assign decode_if.PC = ifetch_rsp_if.PC;
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assign decode_if.ex_type = ex_type;
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assign decode_if.op_type = op_type;
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assign decode_if.op_mod = op_mod;
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assign decode_if.wb = wb;
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assign decode_if.rd = rd_r;
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assign decode_if.rs1 = rs1_r;
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assign decode_if.rs2 = rs2_r;
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assign decode_if.rs3 = rs3_r;
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assign decode_if.imm = imm;
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assign decode_if.use_PC = use_PC;
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assign decode_if.use_imm = use_imm;
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///////////////////////////////////////////////////////////////////////////
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wire ifetch_rsp_fire = ifetch_rsp_if.valid && ifetch_rsp_if.ready;
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assign join_if.valid = ifetch_rsp_fire && is_join;
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assign join_if.wid = ifetch_rsp_if.wid;
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assign wstall_if.valid = ifetch_rsp_fire;
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assign wstall_if.wid = ifetch_rsp_if.wid;
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assign wstall_if.stalled = is_wstall;
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assign ifetch_rsp_if.ready = decode_if.ready;
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`ifdef PERF_ENABLE
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wire [$clog2(`NUM_THREADS+1)-1:0] perf_loads_per_cycle;
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wire [$clog2(`NUM_THREADS+1)-1:0] perf_stores_per_cycle;
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wire [$clog2(`NUM_THREADS+1)-1:0] perf_branches_per_cycle;
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wire [`NUM_THREADS-1:0] perf_loads_per_mask = decode_if.tmask & {`NUM_THREADS{decode_if.ex_type == `EX_LSU && `INST_LSU_IS_MEM(decode_if.op_mod) && decode_if.wb}};
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wire [`NUM_THREADS-1:0] perf_stores_per_mask = decode_if.tmask & {`NUM_THREADS{decode_if.ex_type == `EX_LSU && `INST_LSU_IS_MEM(decode_if.op_mod) && ~decode_if.wb}};
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wire [`NUM_THREADS-1:0] perf_branches_per_mask = decode_if.tmask & {`NUM_THREADS{decode_if.ex_type == `EX_ALU && `INST_ALU_IS_BR(decode_if.op_mod)}};
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`POP_COUNT(perf_loads_per_cycle, perf_loads_per_mask);
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`POP_COUNT(perf_stores_per_cycle, perf_stores_per_mask);
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`POP_COUNT(perf_branches_per_cycle, perf_branches_per_mask);
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reg [`PERF_CTR_BITS-1:0] perf_loads;
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reg [`PERF_CTR_BITS-1:0] perf_stores;
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reg [`PERF_CTR_BITS-1:0] perf_branches;
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always @(posedge clk) begin
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if (reset) begin
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perf_loads <= 0;
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perf_stores <= 0;
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perf_branches <= 0;
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end else begin
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if (decode_if.valid && decode_if.ready) begin
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perf_loads <= perf_loads + `PERF_CTR_BITS'(perf_loads_per_cycle);
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perf_stores <= perf_stores + `PERF_CTR_BITS'(perf_stores_per_cycle);
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perf_branches <= perf_branches + `PERF_CTR_BITS'(perf_branches_per_cycle);
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end
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end
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end
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assign perf_decode_if.loads = perf_loads;
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assign perf_decode_if.stores = perf_stores;
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assign perf_decode_if.branches = perf_branches;
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`endif
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`ifdef DBG_TRACE_CORE_PIPELINE
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always @(posedge clk) begin
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if (decode_if.valid && decode_if.ready) begin
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dpi_trace("%d: core%0d-decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC);
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trace_ex_type(decode_if.ex_type);
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dpi_trace(", op=");
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trace_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod);
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dpi_trace(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b (#%0d)\n",
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decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.use_PC, decode_if.use_imm, decode_if.uuid);
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end
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end
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`endif
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endmodule |