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68 lines
No EOL
1.5 KiB
Systemverilog
68 lines
No EOL
1.5 KiB
Systemverilog
`include "VX_define.vh"
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module VX_fetch #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_fetch
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input wire clk,
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input wire reset,
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// Icache interface
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VX_icache_req_if.master icache_req_if,
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VX_icache_rsp_if.slave icache_rsp_if,
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// inputs
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VX_wstall_if.slave wstall_if,
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VX_join_if.slave join_if,
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VX_branch_ctl_if.slave branch_ctl_if,
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VX_warp_ctl_if.slave warp_ctl_if,
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// outputs
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VX_ifetch_rsp_if.master ifetch_rsp_if,
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// csr interface
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VX_fetch_to_csr_if.master fetch_to_csr_if,
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// busy status
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output wire busy
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);
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VX_ifetch_req_if ifetch_req_if();
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VX_warp_sched #(
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.CORE_ID(CORE_ID)
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) warp_sched (
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`SCOPE_BIND_VX_fetch_warp_sched
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.clk (clk),
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.reset (reset),
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.warp_ctl_if (warp_ctl_if),
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.wstall_if (wstall_if),
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.join_if (join_if),
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.branch_ctl_if (branch_ctl_if),
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.ifetch_req_if (ifetch_req_if),
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.fetch_to_csr_if (fetch_to_csr_if),
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.busy (busy)
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);
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VX_icache_stage #(
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.CORE_ID(CORE_ID)
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) icache_stage (
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`SCOPE_BIND_VX_fetch_icache_stage
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.clk (clk),
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.reset (reset),
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.icache_rsp_if (icache_rsp_if),
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.icache_req_if (icache_req_if),
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.ifetch_req_if (ifetch_req_if),
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.ifetch_rsp_if (ifetch_rsp_if)
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);
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endmodule |