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62 lines
No EOL
1.4 KiB
Systemverilog
62 lines
No EOL
1.4 KiB
Systemverilog
`ifndef VX_GPU_REQ_IF
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`define VX_GPU_REQ_IF
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`include "VX_define.vh"
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interface VX_gpu_req_if();
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wire valid;
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wire [`UUID_BITS-1:0] uuid;
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] tmask;
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wire [31:0] PC;
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wire [31:0] next_PC;
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wire [`INST_GPU_BITS-1:0] op_type;
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wire [`INST_MOD_BITS-1:0] op_mod;
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wire [`NT_BITS-1:0] tid;
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wire [`NUM_THREADS-1:0][31:0] rs1_data;
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wire [`NUM_THREADS-1:0][31:0] rs2_data;
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wire [`NUM_THREADS-1:0][31:0] rs3_data;
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wire [`NR_BITS-1:0] rd;
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wire wb;
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wire ready;
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modport master (
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output valid,
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output uuid,
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output wid,
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output tmask,
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output PC,
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output next_PC,
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output op_type,
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output op_mod,
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output tid,
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output rs1_data,
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output rs2_data,
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output rs3_data,
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output rd,
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output wb,
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input ready
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);
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modport slave (
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input valid,
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input uuid,
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input wid,
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input tmask,
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input PC,
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input next_PC,
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input op_type,
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input op_mod,
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input tid,
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input rs1_data,
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input rs2_data,
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input rs3_data,
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input rd,
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input wb,
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output ready
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);
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endinterface
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`endif |