vortex/hw/rtl/interfaces/VX_mem_rsp_if.sv
2021-09-29 04:48:53 -04:00

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573 B
Systemverilog

`ifndef VX_MEM_RSP_IF
`define VX_MEM_RSP_IF
`include "../cache/VX_cache_define.vh"
interface VX_mem_rsp_if #(
parameter DATA_WIDTH = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [DATA_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
modport master (
output valid,
output data,
output tag,
input ready
);
modport slave (
input valid,
input data,
input tag,
output ready
);
endinterface
`endif