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29 lines
No EOL
564 B
Systemverilog
29 lines
No EOL
564 B
Systemverilog
`ifndef VX_TEX_CSR_IF
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`define VX_TEX_CSR_IF
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`include "VX_define.vh"
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interface VX_tex_csr_if ();
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wire write_enable;
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wire [`CSR_ADDR_BITS-1:0] write_addr;
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wire [31:0] write_data;
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wire [`UUID_BITS-1:0] write_uuid;
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modport master (
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output write_enable,
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output write_addr,
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output write_data,
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output write_uuid
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);
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modport slave (
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input write_enable,
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input write_addr,
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input write_data,
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input write_uuid
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);
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endinterface
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`endif |