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68 lines
No EOL
1.9 KiB
Systemverilog
68 lines
No EOL
1.9 KiB
Systemverilog
`include "VX_platform.vh"
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module VX_stream_demux #(
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parameter NUM_REQS = 1,
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parameter LANES = 1,
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parameter DATAW = 1,
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parameter BUFFERED = 0,
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parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire [LANES-1:0][LOG_NUM_REQS-1:0] sel_in,
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input wire [LANES-1:0] valid_in,
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input wire [LANES-1:0][DATAW-1:0] data_in,
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output wire [LANES-1:0] ready_in,
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output wire [NUM_REQS-1:0][LANES-1:0] valid_out,
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output wire [NUM_REQS-1:0][LANES-1:0][DATAW-1:0] data_out,
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input wire [NUM_REQS-1:0][LANES-1:0] ready_out
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);
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if (NUM_REQS > 1) begin
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for (genvar j = 0; j < LANES; ++j) begin
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reg [NUM_REQS-1:0] valid_in_sel;
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wire [NUM_REQS-1:0] ready_in_sel;
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always @(*) begin
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valid_in_sel = '0;
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valid_in_sel[sel_in[j]] = valid_in[j];
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end
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assign ready_in[j] = ready_in_sel[sel_in[j]];
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for (genvar i = 0; i < NUM_REQS; i++) begin
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VX_skid_buffer #(
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.DATAW (DATAW),
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.PASSTHRU (0 == BUFFERED),
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.OUT_REG (2 == BUFFERED)
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) out_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (valid_in_sel[i]),
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.data_in (data_in[j]),
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.ready_in (ready_in_sel[i]),
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.valid_out (valid_out[i][j]),
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.data_out (data_out[i][j]),
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.ready_out (ready_out[i][j])
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);
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end
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end
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (sel_in)
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assign valid_out = valid_in;
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assign data_out = data_in;
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assign ready_in = ready_out;
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end
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endmodule |