mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-06-28 17:43:24 -04:00
840 lines
24 KiB
C++
840 lines
24 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <iostream>
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#include <string>
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#include <stdlib.h>
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#include <string.h>
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#include <iomanip>
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#include <vector>
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#include <unordered_map>
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#include <util.h>
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#include "debug.h"
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#include "types.h"
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#include "emulator.h"
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#include "arch.h"
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#include "instr.h"
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using namespace vortex;
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static const std::unordered_map<Opcode, InstType> sc_instTable = {
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{Opcode::R, InstType::R},
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{Opcode::L, InstType::I},
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{Opcode::I, InstType::I},
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{Opcode::S, InstType::S},
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{Opcode::B, InstType::B},
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{Opcode::LUI, InstType::U},
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{Opcode::AUIPC, InstType::U},
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{Opcode::JAL, InstType::J},
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{Opcode::JALR, InstType::I},
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{Opcode::SYS, InstType::I},
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{Opcode::FENCE, InstType::I},
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{Opcode::AMO, InstType::R},
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{Opcode::FL, InstType::I},
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{Opcode::FS, InstType::S},
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{Opcode::FCI, InstType::R},
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{Opcode::FMADD, InstType::R4},
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{Opcode::FMSUB, InstType::R4},
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{Opcode::FMNMADD, InstType::R4},
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{Opcode::FMNMSUB, InstType::R4},
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{Opcode::VSET, InstType::V},
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{Opcode::EXT1, InstType::R},
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{Opcode::EXT2, InstType::R4},
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{Opcode::R_W, InstType::R},
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{Opcode::I_W, InstType::I}
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};
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static const char* op_string(const Instr &instr) {
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auto opcode = instr.getOpcode();
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auto funct2 = instr.getFunct2();
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auto funct3 = instr.getFunct3();
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auto funct7 = instr.getFunct7();
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auto rd = instr.getDestReg();
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auto rs1 = instr.getSrcReg(1);
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auto imm = instr.getImm();
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switch (opcode) {
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case Opcode::LUI: return "LUI";
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case Opcode::AUIPC: return "AUIPC";
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case Opcode::R:
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if (funct7 == 0x7) {
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if (funct3 == 0x5) {
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return "CZERO.EQZ";
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} else
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if (funct3 == 0x7) {
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return "CZERO.NEZ";
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} else {
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std::abort();
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}
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} else
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if (funct7 & 0x1) {
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switch (funct3) {
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case 0: return "MUL";
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case 1: return "MULH";
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case 2: return "MULHSU";
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case 3: return "MULHU";
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case 4: return "DIV";
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case 5: return "DIVU";
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case 6: return "REM";
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case 7: return "REMU";
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default:
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std::abort();
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}
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} else {
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switch (funct3) {
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case 0: return (funct7 & 0x20) ? "SUB" : "ADD";
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case 1: return "SLL";
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case 2: return "SLT";
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case 3: return "SLTU";
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case 4: return "XOR";
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case 5: return (funct7 & 0x20) ? "SRA" : "SRL";
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case 6: return "OR";
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case 7: return "AND";
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default:
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std::abort();
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}
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}
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case Opcode::I:
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switch (funct3) {
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case 0: return "ADDI";
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case 1: return "SLLI";
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case 2: return "SLTI";
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case 3: return "SLTIU";
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case 4: return "XORI";
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case 5: return (funct7 & 0x20) ? "SRAI" : "SRLI";
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case 6: return "ORI";
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case 7: return "ANDI";
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default:
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std::abort();
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}
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case Opcode::B:
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switch (funct3) {
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case 0: return "BEQ";
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case 1: return "BNE";
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case 4: return "BLT";
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case 5: return "BGE";
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case 6: return "BLTU";
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case 7: return "BGEU";
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default:
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std::abort();
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}
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case Opcode::JAL: return "JAL";
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case Opcode::JALR: return "JALR";
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case Opcode::L:
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switch (funct3) {
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case 0: return "LB";
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case 1: return "LH";
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case 2: return "LW";
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case 3: return "LD";
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case 4: return "LBU";
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case 5: return "LHU";
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case 6: return "LWU";
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default:
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std::abort();
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}
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case Opcode::S:
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switch (funct3) {
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case 0: return "SB";
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case 1: return "SH";
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case 2: return "SW";
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case 3: return "SD";
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default:
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std::abort();
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}
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case Opcode::R_W:
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if (funct7 & 0x1){
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switch (funct3) {
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case 0: return "MULW";
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case 4: return "DIVW";
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case 5: return "DIVUW";
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case 6: return "REMW";
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case 7: return "REMUW";
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default:
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std::abort();
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}
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} else {
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switch (funct3) {
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case 0: return (funct7 & 0x20) ? "SUBW" : "ADDW";
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case 1: return "SLLW";
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case 5: return (funct7 & 0x20) ? "SRAW" : "SRLW";
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default:
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std::abort();
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}
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}
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case Opcode::I_W:
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switch (funct3) {
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case 0: return "ADDIW";
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case 1: return "SLLIW";
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case 5: return (funct7 & 0x20) ? "SRAIW" : "SRLIW";
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default:
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std::abort();
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}
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case Opcode::SYS:
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switch (funct3) {
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case 0:
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switch (imm) {
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case 0x000: return "ECALL";
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case 0x001: return "EBREAK";
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case 0x002: return "URET";
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case 0x102: return "SRET";
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case 0x302: return "MRET";
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default:
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std::abort();
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}
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case 1: return "CSRRW";
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case 2: return "CSRRS";
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case 3: return "CSRRC";
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case 5: return "CSRRWI";
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case 6: return "CSRRSI";
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case 7: return "CSRRCI";
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default:
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std::abort();
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}
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case Opcode::FENCE: return "FENCE";
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case Opcode::FL:
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switch (funct3) {
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case 0x2: return "FLW";
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case 0x3: return "FLD";
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case 0x0: return "VL8";
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case 0x5: return "VL16";
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case 0x6: return "VL32";
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case 0x7: return "VL64";
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default:
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std::cout << "Could not decode float/vector load with funct3: " << funct3 << std::endl;
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std::abort();
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}
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case Opcode::FS:
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switch (funct3) {
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case 0x1: return "VS";
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case 0x2: return "FSW";
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case 0x3: return "FSD";
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case 0x0: return "VS8";
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case 0x5: return "VS16";
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case 0x6: return "VS32";
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case 0x7: return "VS64";
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default:
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std::cout << "Could not decode float/vector store with funct3: " << funct3 << std::endl;
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std::abort();
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}
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case Opcode::AMO: {
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auto amo_type = funct7 >> 2;
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switch (funct3) {
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case 0x2:
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switch (amo_type) {
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case 0x00: return "AMOADD.W";
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case 0x01: return "AMOSWAP.W";
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case 0x02: return "LR.W";
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case 0x03: return "SC.W";
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case 0x04: return "AMOXOR.W";
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case 0x08: return "AMOOR.W";
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case 0x0c: return "AMOAND.W";
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case 0x10: return "AMOMIN.W";
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case 0x14: return "AMOMAX.W";
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case 0x18: return "AMOMINU.W";
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case 0x1c: return "AMOMAXU.W";
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default:
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std::abort();
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}
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case 0x3:
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switch (amo_type) {
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case 0x00: return "AMOADD.D";
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case 0x01: return "AMOSWAP.D";
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case 0x02: return "LR.D";
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case 0x03: return "SC.D";
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case 0x04: return "AMOXOR.D";
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case 0x08: return "AMOOR.D";
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case 0x0c: return "AMOAND.D";
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case 0x10: return "AMOMIN.D";
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case 0x14: return "AMOMAX.D";
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case 0x18: return "AMOMINU.D";
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case 0x1c: return "AMOMAXU.D";
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default:
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std::abort();
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}
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default:
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std::abort();
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}
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}
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case Opcode::FCI:
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switch (funct7) {
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case 0x00: return "FADD.S";
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case 0x01: return "FADD.D";
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case 0x04: return "FSUB.S";
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case 0x05: return "FSUB.D";
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case 0x08: return "FMUL.S";
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case 0x09: return "FMUL.D";
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case 0x0c: return "FDIV.S";
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case 0x0d: return "FDIV.D";
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case 0x2c: return "FSQRT.S";
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case 0x2d: return "FSQRT.D";
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case 0x10:
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switch (funct3) {
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case 0: return "FSGNJ.S";
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case 1: return "FSGNJN.S";
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case 2: return "FSGNJX.S";
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default:
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std::abort();
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}
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case 0x11:
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switch (funct3) {
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case 0: return "FSGNJ.D";
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case 1: return "FSGNJN.D";
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case 2: return "FSGNJX.D";
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default:
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std::abort();
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}
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case 0x14:
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switch (funct3) {
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case 0: return "FMIN.S";
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case 1: return "FMAX.S";
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default:
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std::abort();
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}
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case 0x15:
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switch (funct3) {
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case 0: return "FMIN.D";
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case 1: return "FMAX.D";
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default:
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std::abort();
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}
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case 0x20: return "FCVT.S.D";
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case 0x21: return "FCVT.D.S";
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case 0x50:
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switch (funct3) {
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case 0: return "FLE.S";
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case 1: return "FLT.S";
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case 2: return "FEQ.S";
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default:
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std::abort();
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}
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case 0x51:
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switch (funct3) {
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case 0: return "FLE.D";
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case 1: return "FLT.D";
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case 2: return "FEQ.D";
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default:
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std::abort();
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}
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case 0x60:
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switch (rs1.idx) {
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case 0: return "FCVT.W.S";
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case 1: return "FCVT.WU.S";
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case 2: return "FCVT.L.S";
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case 3: return "FCVT.LU.S";
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default:
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std::abort();
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}
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case 0x61:
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switch (rs1.idx) {
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case 0: return "FCVT.W.D";
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case 1: return "FCVT.WU.D";
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case 2: return "FCVT.L.D";
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case 3: return "FCVT.LU.D";
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default:
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std::abort();
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}
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case 0x68:
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switch (rs1.idx) {
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case 0: return "FCVT.S.W";
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case 1: return "FCVT.S.WU";
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case 2: return "FCVT.S.L";
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case 3: return "FCVT.S.LU";
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default:
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std::abort();
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}
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case 0x69:
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switch (rs1.idx) {
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case 0: return "FCVT.D.W";
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case 1: return "FCVT.D.WU";
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case 2: return "FCVT.D.L";
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case 3: return "FCVT.D.LU";
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default:
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std::abort();
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}
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case 0x70: return funct3 ? "FCLASS.S" : "FMV.X.S";
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case 0x71: return funct3 ? "FCLASS.D" : "FMV.X.D";
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case 0x78: return "FMV.S.X";
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case 0x79: return "FMV.D.X";
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default:
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std::abort();
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}
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case Opcode::FMADD: return funct2 ? "FMADD.D" : "FMADD.S";
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case Opcode::FMSUB: return funct2 ? "FMSUB.D" : "FMSUB.S";
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case Opcode::FMNMADD: return funct2 ? "FNMADD.D" : "FNMADD.S";
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case Opcode::FMNMSUB: return funct2 ? "FNMSUB.D" : "FNMSUB.S";
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case Opcode::VSET: return "VSET";
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case Opcode::EXT1:
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switch (funct7) {
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case 0:
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switch (funct3) {
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case 0: return "TMC";
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case 1: return "WSPAWN";
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case 2: return rs1.idx ? "SPLIT.N" : "SPLIT";
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case 3: return "JOIN";
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case 4: return "BAR";
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case 5: return rd.idx ? "PRED.N" : "PRED";
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default:
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std::abort();
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}
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case 1:
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switch (funct3) {
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case 0: // gfx reserved
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std::abort();
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default:
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std::abort();
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}
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#ifdef EXT_TPU_ENABLE
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case 2:
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switch (funct3) {
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case 0: return "HMMA844";
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default:
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std::abort();
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}
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#endif
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default:
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std::abort();
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}
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case Opcode::EXT2:
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switch(funct3) {
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case 0: // gfx reserved
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case 1: // gfx reserved
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std::abort();
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default:
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std::abort();
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}
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default:
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std::abort();
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}
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}
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#ifdef EXT_V_ENABLE
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inline void print_vec_attr(std::ostream &os, const Instr &instr) {
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uint32_t mask = instr.getVattrMask();
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if (mask & vattr_vlswidth)
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os << ", width:" << instr.getVlsWidth();
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if (mask & vattr_vmop)
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os << ", mop:" << instr.getVmop();
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if (mask & vattr_vumop)
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os << ", umop:" << instr.getVumop();
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if (mask & vattr_vnf)
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os << ", nf:" << instr.getVnf();
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if (mask & vattr_vmask)
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os << ", vmask:" << instr.getVmask();
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if (mask & vattr_vs3)
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os << ", vs3:" << instr.getVs3();
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if (mask & vattr_zimm)
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os << ", zimm:" << instr.getZimm();
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if (mask & vattr_vediv)
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os << ", ediv:" << instr.getVediv();
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}
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#endif
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namespace vortex {
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std::ostream &operator<<(std::ostream &os, const Instr &instr) {
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os << op_string(instr);
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int sep = 0;
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auto rd = instr.getDestReg();
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if (rd.type != RegType::None) {
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if (sep++ != 0) { os << ", "; } else { os << " "; }
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os << rd;
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}
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for (uint32_t i = 0; i < instr.getNumSrcRegs(); ++i) {
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auto rs = instr.getSrcReg(i);
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if (rs.type != RegType::None) {
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if (sep++ != 0) { os << ", "; } else { os << " "; }
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os << rs;
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}
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}
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if (instr.hasImm()) {
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if (sep++ != 0) { os << ", "; } else { os << " "; }
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os << "0x" << std::hex << instr.getImm() << std::dec;
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}
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if (instr.getOpcode() == Opcode::SYS && instr.getFunct3() >= 5) {
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// CSRs with immediate values
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if (sep++ != 0) { os << ", "; } else { os << " "; }
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os << "0x" << std::hex << instr.getSrcReg(0).idx;
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}
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#ifdef EXT_V_ENABLE
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// Log vector-specific attributes
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if (instr.getVattrMask() != 0) {
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print_vec_attr(os, instr);
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}
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#endif
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return os;
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}
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}
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Instr::Ptr Emulator::decode(uint32_t code) const {
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auto instr = std::allocate_shared<Instr>(instr_pool_);
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auto op = Opcode((code >> shift_opcode) & mask_opcode);
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instr->setOpcode(op);
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auto funct2 = (code >> shift_funct2) & mask_funct2;
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auto funct3 = (code >> shift_funct3) & mask_funct3;
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auto funct6 = (code >> shift_funct6) & mask_funct6;
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auto funct7 = (code >> shift_funct7) & mask_funct7;
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__unused(funct6);
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auto rd = (code >> shift_rd) & mask_reg;
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auto rs1 = (code >> shift_rs1) & mask_reg;
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auto rs2 = (code >> shift_rs2) & mask_reg;
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auto rs3 = (code >> shift_rs3) & mask_reg;
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auto op_it = sc_instTable.find(op);
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if (op_it == sc_instTable.end()) {
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std::cerr << "Error: invalid opcode: 0x" << std::hex << static_cast<int>(op) << std::dec << std::endl;
|
|
return nullptr;
|
|
}
|
|
|
|
auto iType = op_it->second;
|
|
if (op == Opcode::FL || op == Opcode::FS) {
|
|
if (funct3 != 0x2 && funct3 != 0x3) {
|
|
iType = InstType::V;
|
|
}
|
|
}
|
|
|
|
switch (iType) {
|
|
case InstType::R:
|
|
switch (op) {
|
|
case Opcode::FCI:
|
|
switch (funct7) {
|
|
case 0x20: // FCVT.S.D
|
|
case 0x21: // FCVT.D.S
|
|
instr->setDestReg(rd, RegType::Float);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
break;
|
|
case 0x2c: // FSQRT.S
|
|
case 0x2d: // FSQRT.D
|
|
instr->setDestReg(rd, RegType::Float);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
break;
|
|
case 0x50: // FLE.S, FLT.S, FEQ.S
|
|
case 0x51: // FLE.D, FLT.D, FEQ.D
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
instr->addSrcReg(rs2, RegType::Float);
|
|
break;
|
|
case 0x60: // FCVT.W.D, FCVT.WU.D, FCVT.L.D, FCVT.LU.D
|
|
case 0x61: // FCVT.WU.S, FCVT.W.S, FCVT.L.S, FCVT.LU.S
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
instr->addSrcReg(rs2, RegType::None);
|
|
break;
|
|
case 0x68: // FCVT.S.W, FCVT.S.WU, FCVT.S.L, FCVT.S.LU
|
|
case 0x69: // FCVT.D.W, FCVT.D.WU, FCVT.D.L, FCVT.D.LU
|
|
instr->setDestReg(rd, RegType::Float);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::None);
|
|
break;
|
|
case 0x70: // FCLASS.S, FMV.X.S
|
|
case 0x71: // FCLASS.D, FMV.X.D
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
break;
|
|
case 0x78: // FMV.S.X
|
|
case 0x79: // FMV.D.X
|
|
instr->setDestReg(rd, RegType::Float);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
break;
|
|
default:
|
|
instr->setDestReg(rd, RegType::Float);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
instr->addSrcReg(rs2, RegType::Float);
|
|
break;
|
|
}
|
|
break;
|
|
case Opcode::EXT1:
|
|
switch (funct7) {
|
|
case 0:
|
|
switch (funct3) {
|
|
case 0: // TMC
|
|
case 3: // JOIN
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
break;
|
|
case 1: // WSPAWN
|
|
case 4: // BAR
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::Integer);
|
|
break;
|
|
case 5: // PRED
|
|
instr->setDestReg(rd, RegType::None);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::Integer);
|
|
break;
|
|
case 2: // SPLIT
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::None);
|
|
break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
break;
|
|
#ifdef EXT_TPU_ENABLE
|
|
case 2: {
|
|
switch (funct3) {
|
|
case 0: { // HMMA844
|
|
uint32_t fmt = rd;
|
|
uint32_t steps = rs1 >> 1;
|
|
uint32_t step = steps % 4;
|
|
uint32_t set = steps / 4;
|
|
uint32_t rd_pair = rs1 & 0x1;
|
|
uint32_t use_d = rs2;
|
|
uint32_t base_rd = (use_d ? 16 : 0) + (step * 2 + rd_pair); // C/D
|
|
uint32_t base_rs1 = 8 + set; // A
|
|
uint32_t base_rs2 = 24 + set; // B
|
|
uint32_t base_rs3 = 0 + step; // C
|
|
instr->setImm((fmt << 2) + step); // fmt + step
|
|
instr->setDestReg(base_rd, RegType::Float);
|
|
instr->addSrcReg(base_rs1, RegType::Float);
|
|
instr->addSrcReg(base_rs2, RegType::Float);
|
|
instr->addSrcReg(base_rs3, RegType::Float);
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
} break;
|
|
#endif
|
|
default:
|
|
std::abort();
|
|
}
|
|
break;
|
|
default:
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::Integer);
|
|
break;
|
|
}
|
|
instr->setfunct3(funct3);
|
|
instr->setfunct7(funct7);
|
|
break;
|
|
|
|
case InstType::I: {
|
|
switch (op) {
|
|
case Opcode::I:
|
|
case Opcode::I_W:
|
|
case Opcode::JALR:
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->setfunct3(funct3);
|
|
if (funct3 == 0x1 || funct3 == 0x5) {
|
|
// Shift instructions
|
|
auto shamt = rs2; // uint5
|
|
#if (XLEN == 64)
|
|
if (op == Opcode::I) {
|
|
// uint6
|
|
shamt |= ((funct7 & 0x1) << 5);
|
|
}
|
|
#endif
|
|
instr->setImm(shamt);
|
|
instr->setfunct7(funct7);
|
|
} else {
|
|
auto imm = code >> shift_rs2;
|
|
instr->setImm(sext(imm, width_i_imm));
|
|
}
|
|
break;
|
|
case Opcode::L:
|
|
case Opcode::FL: {
|
|
instr->setDestReg(rd, (op == Opcode::FL) ? RegType::Float : RegType::Integer);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->setfunct3(funct3);
|
|
auto imm = code >> shift_rs2;
|
|
instr->setImm(sext(imm, width_i_imm));
|
|
} break;
|
|
case Opcode::FENCE:
|
|
instr->setfunct3(funct3);
|
|
instr->setImm(code >> shift_rs2);
|
|
break;
|
|
case Opcode::SYS:
|
|
if (funct3 != 0) {
|
|
// CSR instructions
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
instr->setfunct3(funct3);
|
|
if (funct3 < 5) {
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
} else {
|
|
// zimm
|
|
instr->addSrcReg(rs1, RegType::None);
|
|
}
|
|
instr->setImm(code >> shift_rs2);
|
|
} else {
|
|
// ECALL/EBREACK instructions
|
|
instr->setImm(code >> shift_rs2);
|
|
}
|
|
break;
|
|
default:
|
|
std::abort();
|
|
break;
|
|
}
|
|
} break;
|
|
case InstType::S: {
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, (op == Opcode::FS) ? RegType::Float : RegType::Integer);
|
|
instr->setfunct3(funct3);
|
|
auto imm = (funct7 << width_reg) | rd;
|
|
instr->setImm(sext(imm, width_i_imm));
|
|
} break;
|
|
|
|
case InstType::B: {
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::Integer);
|
|
instr->setfunct3(funct3);
|
|
auto bit_11 = rd & 0x1;
|
|
auto bits_4_1 = rd >> 1;
|
|
auto bit_10_5 = funct7 & 0x3f;
|
|
auto bit_12 = funct7 >> 6;
|
|
auto imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
|
|
instr->setImm(sext(imm, width_i_imm+1));
|
|
} break;
|
|
|
|
case InstType::U: {
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
auto imm = (code >> shift_funct3) << shift_funct3;
|
|
instr->setImm(imm);
|
|
} break;
|
|
|
|
case InstType::J: {
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
auto unordered = code >> shift_funct3;
|
|
auto bits_19_12 = unordered & 0xff;
|
|
auto bit_11 = (unordered >> 8) & 0x1;
|
|
auto bits_10_1 = (unordered >> 9) & 0x3ff;
|
|
auto bit_20 = (unordered >> 19) & 0x1;
|
|
auto imm = (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
|
|
instr->setImm(sext(imm, width_j_imm+1));
|
|
} break;
|
|
|
|
case InstType::R4: {
|
|
instr->setDestReg(rd, RegType::Float);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
instr->addSrcReg(rs2, RegType::Float);
|
|
instr->addSrcReg(rs3, RegType::Float);
|
|
instr->setfunct2(funct2);
|
|
instr->setfunct3(funct3);
|
|
} break;
|
|
|
|
#ifdef EXT_V_ENABLE
|
|
case InstType::V:
|
|
switch (op) {
|
|
case Opcode::VSET: {
|
|
instr->setfunct3(funct3);
|
|
switch (funct3) {
|
|
case 0: { // OPIVV
|
|
instr->setDestReg(rd, RegType::Vector);
|
|
instr->addSrcReg(rs1, RegType::Vector);
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setfunct6(funct6);
|
|
} break;
|
|
case 1: { // OPFVV
|
|
instr->setDestReg(rd, (funct6 == 16) ? RegType::Float : RegType::Vector);
|
|
instr->addSrcReg(rs1, RegType::Vector);
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setfunct6(funct6);
|
|
} break;
|
|
case 2: { // OPMVV
|
|
instr->setDestReg(rd, (funct6 == 16) ? RegType::Integer : RegType::Vector);
|
|
instr->addSrcReg(rs1, RegType::Vector);
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setfunct6(funct6);
|
|
} break;
|
|
case 3: { // OPIVI
|
|
instr->setDestReg(rd, RegType::Vector);
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
instr->setImm(rs1);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setfunct6(funct6);
|
|
} break;
|
|
case 4: { // OPIVX
|
|
instr->setDestReg(rd, RegType::Vector);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setfunct6(funct6);
|
|
} break;
|
|
case 5: { // OPFVF
|
|
instr->setDestReg(rd, RegType::Vector);
|
|
instr->addSrcReg(rs1, RegType::Float);
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setfunct6(funct6);
|
|
} break;
|
|
case 6: { // POMVX
|
|
instr->setDestReg(rd, (funct6 == 16) ? RegType::Integer : RegType::Vector);
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setfunct6(funct6);
|
|
} break;
|
|
case 7: {
|
|
instr->setDestReg(rd, RegType::Integer);
|
|
if ((code >> 30) == 0b10) {
|
|
// vsetvl
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
instr->addSrcReg(rs2, RegType::Integer);
|
|
} else {
|
|
auto zimm = (code >> shift_rs2) & mask_v_zimm;
|
|
instr->setZimm(zimm);
|
|
if ((code >> 30) == 0b11) {
|
|
// vsetivli
|
|
instr->setImm(rs1);
|
|
} else {
|
|
// vsetvli
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
}
|
|
}
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
} break;
|
|
case Opcode::FL:
|
|
case Opcode::FS: {
|
|
instr->addSrcReg(rs1, RegType::Integer);
|
|
uint32_t vmop = (code >> shift_vmop) & 0b11;
|
|
switch (vmop) {
|
|
case 0b00:
|
|
instr->setVumop(rs2);
|
|
break;
|
|
case 0b10:
|
|
instr->addSrcReg(rs2, RegType::Integer);
|
|
break;
|
|
case 0b01:
|
|
case 0b11:
|
|
instr->addSrcReg(rs2, RegType::Vector);
|
|
break;
|
|
}
|
|
if (op == Opcode::FL) {
|
|
instr->setDestReg(rd, RegType::Vector);
|
|
} else {
|
|
instr->addSrcReg(rd, RegType::Vector);
|
|
}
|
|
instr->setVlsWidth(funct3);
|
|
instr->setVmask((code >> shift_funct7) & 0x1);
|
|
instr->setVmop(vmop);
|
|
instr->setVnf((code >> shift_vnf) & mask_funct3);
|
|
} break;
|
|
default:
|
|
std::abort();
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
std::abort();
|
|
}
|
|
|
|
return instr;
|
|
}
|